CC BY 4.0 UnportedLopacinski, LukaszBrzozowski, MarcinKraemer, Rolf2023-02-062023-02-062017https://oa.tib.eu/renate/handle/123456789/11294http://dx.doi.org/10.34657/10330This paper presents a hardware processor for 100Gbps wireless data link layer. A serial Reed-Solomon decoder requires a clock of 12.5GHz to fulfill timings constraints of the transmission. Receiving a single Ethernet frame on a 100 Gbps physical layer may be faster than accessing DDR3 memory. Processing so fast streams on a state-of-the-art FPGA (field programmable gate arrays) requires a dedicated approach. Thus, the paper presents lightweight RS FEC engine, frames fragmentation, aggregation, and a protocol with selective fragment retransmission. The implemented FPGA demonstrator achieves nearly 120 Gbps and accepts bit error rate (BER) up to 2e - 3. Moreover, redundancy added to the frames is adopted according to the channel BER by a dedicated link adaptation algorithm. At the end, ASIC synthesis results are presented including detailed statistics of consumed energy per bit.enghttps://creativecommons.org/licenses/by/4.0/620Consumed energyData link layerHardware processorLink adaptation algorithmPhysical layersReed Solomon decoderState of the artWireless Data linksArticle