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Atomically controlled CVD processing of group IV semiconductors for ultra-large-scale integrations
One of the main requirements for ultra-large-scale integrations (ULSIs) is atomic-order control of process technology. Our concept of atomically controlled processing is based on atomic-order surface reaction control by CVD. By ultraclean low-pressure CVD using SiH4 and GeH4 gases, high-quality low-temperature epitaxial growth of Si1−xGex (100) (x=0–1) with atomically flat surfaces and interfaces on Si(100) is achieved. Self-limiting formation of 1–3 atomic layers of group IV or related atoms in the thermal adsorption and reaction of hydride gases on Si1-xGex (100) are generalized based on the Langmuir-type model. By the Si epitaxial growth on top of the material already-formed on Si(100), N, B and C atoms are confined within about a 1 nm thick layer. In Si cap layer growth on the P atomic layer formed on Si1−xGex (100), segregation of P atoms is suppressed by using Si2H6 instead of SiH4 at a low temperature of 450 °C. Heavy C atomic-layer doping suppresses strain relaxation as well as intermixing between Si and Ge at the Si1−xGex/Si heterointerface. It is confirmed that higher carrier concentration and higher carrier mobility are achieved by atomic-layer doping. These results open the way to atomically controlled technology for ULSIs.
Morphological Evolution of Pit-Patterned Si(001) Substrates Driven by Surface-Energy Reduction
Lateral ordering of heteroepitaxial islands can be conveniently achieved by suitable pit-patterning of the substrate prior to deposition. Controlling shape, orientation, and size of the pits is not trivial as, being metastable, they can significantly evolve during deposition/annealing. In this paper, we exploit a continuum model to explore the typical metastable pit morphologies that can be expected on Si(001), depending on the initial depth/shape. Evolution is predicted using a surface-diffusion model, formulated in a phase-field framework, and tackling surface-energy anisotropy. Results are shown to nicely reproduce typical metastable shapes reported in the literature. Moreover, long time scale evolutions of pit profiles with different depths are found to follow a similar kinetic pathway. The model is also exploited to treat the case of heteroepitaxial growth involving two materials characterized by different facets in their equilibrium Wulff’s shape. This can lead to significant changes in morphologies, such as a rotation of the pit during deposition as evidenced in Ge/Si experiments.
On the electronic properties of a single dislocation
A detailed knowledge of the electronic properties of individual dislocations is necessary for next generation nanodevices. Dislocations are fundamental crystal defects controlling the growth of different nanostructures (nanowires) or appear during device processing. We present a method to record electric properties of single dislocations in thin silicon layers. Results of measurements on single screw dislocations are shown for the first time. Assuming a cross-section area of the dislocation core of about 1 nm2, the current density through a single dislocation is J = 3.8 × 1012 A/cm2 corresponding to a resistivity of ρ ≅ 1 × 10-8 Ω cm. This is about eight orders of magnitude lower than the surrounding silicon matrix. The reason of the supermetallic behavior is the high strain in the cores of the dissociated dislocations modifying the local band structure resulting in high conductive carrier channels along defect cores.
A graphene-based hot electron transistor
We experimentally demonstrate DC functionality of graphene-based hot electron transistors, which we call graphene base transistors (GBT). The fabrication scheme is potentially compatible with silicon technology and can be carried out at the wafer scale with standard silicon technology. The state of the GBTs can be switched by a potential applied to the transistor base, which is made of graphene. Transfer characteristics of the GBTs show ON/OFF current ratios exceeding 104.
Engineering the semiconductor/oxide interaction for stacking twin suppression in single crystalline epitaxial silicon(111)/insulator/Si(111) heterostructures
The integration of alternative semiconductor layers on the Si material platform via oxide heterostructures is of interest to increase the performance and/or functionality of future Si-based integrated circuits. The single crystalline quality of epitaxial (epi) semiconductor-insulator-Si heterostructures is however limited by too high defect densities, mainly due to a lack of knowledge about the fundamental physics of the heteroepitaxy mechanisms at work. To shed light on the physics of stacking twin formation as one of the major defect mechanisms in (111)-oriented fcc-related heterostructures on Si(111), we report a detailed experimental and theoretical study on the structure and defect properties of epi-Si(111)/Y2O 3/Pr2O3/Si(111) heterostructures. Synchrotron radiation-grazing incidence x-ray diffraction (SR-GIXRD) proves that the engineered Y2O3/Pr2O3 buffer dielectric heterostructure on Si(111) allows control of the stacking sequence of the overgrowing single crystalline epi-Si(111) layers. The epitaxy relationship of the epi-Si(111)/insulator/Si(111) heterostructure is characterized by a type A/B/A stacking configuration. Theoretical ab initio calculations show that this stacking sequence control of the heterostructure is mainly achieved by electrostatic interaction effects across the ionic oxide/covalent Si interface (IF). Transmission electron microscopy (TEM) studies detect only a small population of misaligned type B epi-Si(111) stacking twins whose location is limited to the oxide/epiSi IF region. Engineering the oxide/semiconductor IF physics by using tailored oxide systems opens thus a promising approach to grow heterostructures with well-controlled properties. © IOP Publishing Ltd and Deutsche Physikalische Gesellschaft.