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- ItemOn the Impact of Strained PECVD Nitride Layers on Oxide Precipitate Nucleation in Silicon(Pennington, NJ : ECS, 2019) Kissinger, G.; Kot, D.; Costina, I.; Lisker, M.PECVD nitride layers with different layer stress ranging from about 315 MPa to −1735 MPa were deposited on silicon wafers with similar concentration of interstitial oxygen. After a thermal treatment consisting of nucleation at 650°C for 4 h or 8 h followed annealing 780°C 3 h + 1000°C 16 h in nitrogen, the profiles of the oxide precipitate density were investigated. The binding states of hydrogen in the layers was investigated by FTIR. There is a clear effect of the layer stress on oxide precipitate nucleation. The higher the compressive layer stress is the higher is a BMD peak below the front surface. If the nitride layer is removed after the nucleation anneal the BMD peak below the front surface becomes lower. It is possible to model the BMD peak below the surface by vacancy in-diffusion from the silicon/nitride interface. With increasing duration of the nucleation anneal the vacancy injection from the silicon/nitride interface decreases and with increasing compressive layer stress it increases. © The Author(s) 2019.
- ItemInvestigation of the copper gettering mechanism of oxide precipitates in silicon(Pennington, NJ : ECS, 2015) Kissinger, G.; Kot, D.; Klingsporn, M.; Schubert, M.A.; Sattler, A.; Müller, T.One of the reasons why the principal gettering mechanism of copper at oxide precipitates is not yet clarified is that it was not possible to identify the presence and measure the copper concentration in the vicinity of oxide precipitates. To overcome the problem we used a 14.5 nm thick thermal oxide layer as a model system for an oxide precipitate to localize the place where the copper is collected. We also analyzed a plate-like oxide precipitate by EDX and EELS and compared the results with the analysis carried out on the oxide layer. It is demonstrated that both the interface between the oxide precipitate being SiO2 and the silicon matrix and the interface between the thermal oxide and silicon consist of a 2–3 nm thick SiO layer. As the results of these experiments also show that copper segregates at the SiO interface layer of the thermal oxide it is concluded that gettering of copper by oxide precipitates is based on segregation of copper to the SiO interface layer.
- ItemLateral Selective SiGe Growth for Local Dislocation-Free SiGe-on-Insulator Virtual Substrate Fabrication(Pennington, NJ : ECS, 2023) Anand, K.; Schubert, M.A.; Corley-Wiciak, A.A.; Spirito, D.; Corley-Wiciak, C.; Klesse, W.M.; Mai, A.; Tillack, B.; Yamamoto, Y.Dislocation free local SiGe-on-insulator (SGOI) virtual substrate is fabricated using lateral selective SiGe growth by reduced pressure chemical vapor deposition. The lateral selective SiGe growth is performed around a ∼1.25 μm square Si (001) pillar in a cavity formed by HCl vapor phase etching of Si at 850 °C from side of SiO2/Si mesa structure on buried oxide. Smooth root mean square roughness of SiGe surface of 0.14 nm, which is determined by interface roughness between the sacrificially etched Si and the SiO2 cap, is obtained. Uniform Ge content of ∼40% in the laterally grown SiGe is observed. In the Si pillar, tensile strain of ∼0.65% is found which could be due to thermal expansion difference between SiO2 and Si. In the SiGe, tensile strain of ∼1.4% along 〈010〉 direction, which is higher compared to that along 〈110〉 direction, is observed. The tensile strain is induced from both [110] and [−110] directions. Threading dislocations in the SiGe are located only ∼400 nm from Si pillar and stacking faults are running towards 〈110〉 directions, resulting in the formation of a wide dislocation-free area in SiGe along 〈010〉 due to horizontal aspect ratio trapping.
- ItemOn the Impact of Strained PECVD Oxide Layers on Oxide Precipitation in Silicon(Pennington, NJ : ECS, 2019) Kissinger, G.; Kot, D.; Lisker, M.; Sattler, A.PECVD oxide layers with different layer stress ranging from about −305.2 MPa to 39.9 MPa were deposited on silicon wafers with similar concentration of interstitial oxygen. After a thermal treatment consisting of rapid thermal annealing (RTA) and furnace annealing 780°C 3 h + 1000°C 16 h in nitrogen the profiles of the oxide precipitate density were investigated. Supersaturations of self-interstitials as function of layer stress were determined by adjusting modelling results to measured depth profiles of bulk microdefects. The self-interstitial supersaturation generated by RTA at 1250°C and 1175°C at the silicon/oxide interface is increasing linearly with increasing layer stress. Values for self-interstitial supersaturation determined on deposited oxide layers after RTA at 1250°C and 1175°C are very similar to values published for RTO by Sudo et al. An RTA at 1175°C with a PECVD oxide on top of the wafer is a method to effectively suppress oxygen precipitation in silicon wafers. Nucleation anneals carried out at 650°C for 4 h and 8 h did not show any effect of PECVD oxide layers on oxide precipitate nucleation. © The Author(s) 2019.
- ItemEditors' Choice - Precipitation of Suboxides in Silicon, their Role in Gettering of Copper Impurities and Carrier Recombination(Pennington, NJ : ECS, 2020) Kissinger, G.; Kot, D.; Huber, A.; Kretschmer, R.; Müller, T.; Sattler, A.This paper describes a theoretical investigation of the phase composition of oxide precipitates and the corresponding emission of self-interstitials at the minimum of the free energy and their evolution with increasing number of oxygen atoms in the precipitates. The results can explain the compositional evolution of oxide precipitates and the role of self-interstitials therein. The formation of suboxides at the edges of SiO2 precipitates after reaching a critical size can explain several phenomena like gettering of Cu by segregation to the suboxide region and lifetime reduction by recombination of minority carriers in the suboxide. It provides an alternative explanation, based on minimized free energy, to the theory of strained and unstrained plates. A second emphasis was payed to the evolution of the morphology of oxide precipitates. Based on the comparison with results from scanning transmission electron microscopy the sequence of morphology evolution of oxide precipitates was deduced. It turned out that it is opposite to the sequence assumed until now. © 2020 The Author(s). Published on behalf of The Electrochemical Society by IOP Publishing Limited.
- ItemSelective lateral germanium growth for local GeOI fabrication(Pennington, NJ : ECS, 2014) Yamamoto, Yuji; Schubert, Markus Andreas; Reich, Christian; Bernd Tillack, Bernd TillackHigh quality local Germanium-on-oxide (GeOI) wafers are fabricated using selective lateral germanium (Ge) growth technique by a single wafer reduced pressure chemical vapor deposition system. Mesa structures of 300 nm thick epitaxial silicon (Si) interposed by SiO2 cap and buried oxide are prepared. HCl vapor phase etching of Si is performed prior to selective Ge growth to remove a part of the epitaxial Si to form cavity under the mesa. By following selective Ge growth, the cavity was filled. Cross section TEM shows dislocations of Ge which are located near Si / Ge interface only. By plan view TEM, it is shown that the dislocations in Ge which direct to SiO2 cap or to buried-oxide (BOX) are located near the interface of Si and Ge. The dislocations which run parallel to BOX are observed only in [110] and [1–10] direction resulting Ge grown toward [010] direction contains no dislocations. This mechanism is similar to aspect-ratio-trapping but here we are using a horizontal approach, which offers the option to remove the defective areas by standard structuring techniques. A root mean square of roughness of ∼0.2 nm is obtained after the SiO2 cap removal. Tensile strain in the Ge layer is observed due to higher thermal expansion coefficient of Ge compared to Si and SiO2.
- ItemDislocation generation and propagation during flash lamp annealing(Pennington, NJ : ECS, 2015) Kissinger, G.; Kot, D.; Schubert, M.A.; Sattler, A.Dislocation generation and propagation during flash lamp annealing for 20 ms was investigated using wafers with sawed, ground, and etched surfaces. Due to the thermal stress resulting from the temperature profiles generated by the flash pre-existing dislocations propagate into the wafer from both surfaces during flash lamp annealing. A dislocation free zone was observed around 700 μm depth below the surface of a 900 μm thick sawed wafer. The dislocation propagation can be well described by a three-dimensional mechanical model. It was further demonstrated that in wafers being initially free of dislocations no dislocations are generated during flash lamp annealing.