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    Temperature Dependence of Dark Spot Diameters in GaN and AlGaN
    (Weinheim : Wiley-VCH, 2021) Netzel, Carsten; Knauer, Arne; Brunner, Frank; Mogilatenko, Anna; Weyers, Markus
    Threading dislocations in c-plane (Al,Ga)N layers are surrounded by areas with reduced light generation efficiency, called “dark spots.” These areas are observable in luminescence measurements with spatial resolution in the submicrometer range. Dark spots reduce the internal quantum efficiency in single layers and light-emitting devices. In cathodoluminescence measurements, the diameter of dark spots (full width at half maximum [FWHM]) is observed to be 200–250 nm for GaN. It decreases by 30–60% for AlxGa1−xN with x ≈ 0.5. Furthermore, the dark spot diameter increases with increasing temperature from 83 to 300 K in AlGaN, whereas it decreases in GaN. Emission energy mappings around dark spots become less smooth and show sharper features on submicrometer scales at low temperature for AlGaN and, on the contrary, at high temperature for GaN. It is concluded that charge carrier localization dominates the temperature dependence of dark spot diameters and of the emission energy distribution around threading dislocations in AlGaN, whereas the temperature-dependent excitation volume in cathodoluminescence and charge carrier diffusion limited by phonon scattering are the dominant effects in GaN. Consequently, with increasing temperature, nonradiative recombination related to threading dislocations extends to wider regions in AlGaN, whereas it becomes spatially limited in GaN.
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    Analysis of Mechanical Strain in AlGaN/GaN HFETs
    (Weinheim : Wiley-VCH, 2023) Yazdani, Hossein; Graff, Andreas; Simon-Najasek, Michél; Altmann, Frank; Brunner, Frank; Ostermay, Ina; Chevtchenko, Serguei; Würfl, Joachim
    Herein, the influence of mechanical strain induced by passivation layers on the electrical performance of AlGaN/GaN heterostructure field-effect transistor is investigated. We studied the physical mechanism of a threshold voltage (Vth) shift for the monolithically fabricated on/off devices reported earlier by our group. For that, theoretical calculations, simulation-based analysis, and nano-beam electron diffraction (NBED) measurements based on STEM are used. Strain distribution in the gate vicinity of transistors is compared for a SiNx passivation layer with intrinsic stress from ≈0.5 to −1 GPa for normally on and normally off devices, respectively. The strain in epitaxial layers transferred by intrinsic stress of SiNx is quantitatively evaluated using NEBD method. Strain dissimilarity Δε = 0.23% is detected between normally on and normally off devices. Using this method, quantitative correlation between 1.13 V of Vth shift and microscopic strain difference in the epitaxial layers caused by 1.5 GPa intrinsic stress variation in passivation layer is provided. It is showed in this correlation that about half of the reported threshold voltage shift is induced by strain, i.e., by the piezoelectric effect. The rest of Vth shift is caused by the fabrication process. Therefore, various components/mechanisms contributing to the measured Vth shift are distinguished.
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    On the Conduction Properties of Vertical GaN n-Channel Trench MISFETs
    ([New York, NY] : IEEE, 2021) Treidel, Eldad Bahat; Hilt, Oliver; Hoffmann, Veit; Brunner, Frank; Bickel, Nicole; Thies, Andreas; Tetzner, Kornelius; Gargouri, Hassan; Huber, Christian; Donimirski, Konstanty; Wurfl, Joachim
    ON-state conductance properties of vertical GaN n -channel trench MISFETs manufactured on different GaN substrates and having different gate trench orientations are studied up to 200 °C ambient temperature. The best performing devices, with a maximum output current above 4 kA/cm 2 and an area specific ON-state resistance of 1.1 mΩ·cm 2 , are manufactured on ammonothermal GaN substrate with the gate channel parallel to the a-plane of the GaN crystal. The scalability of the devices up to 40 mm gate periphery is investigated and demonstrated. It is found that, in addition to oxide interface traps, the semiconductor border traps in the p-GaN layer limit the available mobile channel electrons and that the channel surface roughness scattering limits the channel mobility. Both strongly depend on the gate trench orientation and on the GaN substrate defect density.
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    Structural and optical properties of (112̅2) InGaN quantum wells compared to (0001) and (112̅0)
    (Milton Park : Taylor & Francis, 2016) Pristovsek, Markus; Han, Yisong; Zhu, Tongtong; Oehler, Fabrice; Tang, Fengzai; Oliver, Rachel A.; Humphreys, Colin J.; Tytko, Darius; Choi, Pyuck-Pa; Raabe, Dierk; Brunner, Frank; Weyers, Markus
    We benchmarked growth, microstructure and photo luminescence (PL) of (112-2) InGaN quantum wells (QWs) against (0001) and (112-0). In incorporation, growth rate and the critical thickness of (112-2) QWs are slightly lower than (0001) QWs, while the In incorporation on (112-0) is reduced by a factor of three. A small step-bunching causes slight fluctuations of the emission wavelength. Transmission electron microscopy as well as atom probe tomography (APT) found very flat interfaces with little In segregation even for 20% In content. APT frequency distribution analysis revealed some deviation from a random InGaN alloy, but not as severe as for (112-0). The slight deviation of (112-2) QWs from an ideal random alloy did not broaden the 300 K PL, the line widths were similar for (112-2) and (0001) while (112-0) QWs were broader. Despite the high structural quality and narrow PL, the integrated PL signal at 300 K was about 4 lower on (112-2) and more than 10 lower on (112-0).
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    Effects of post metallization annealing on Al2O3 atomic layer deposition on n-GaN
    (Bristol : IOP Publ., 2022) Tadmor, Liad; Brusaterra, Enrico; Treidel, Eldad Bahat; Brunner, Frank; Bickel, Nicole; Vandenbroucke, Sofie S. T.; Detavernier, Christophe; Würfl, Joachim; Hilt, Oliver
    The chemical, physical and electrical properties and the robustness of post metallization annealed Al2O3 atomic layers deposited on n-type GaN are investigated in this work. Planar metal insulator capacitors are used to demonstrate a gate-first with following ohmic contacts formation at elevated temperature up to 600 °C process flow. X-ray photoelectron spectroscopy indicates that no new bonds in the Al2O3 layer are formed due to exposure to the elevated annealing temperature. X-ray diffraction measurements show no crystallization of the oxide layer. Atomic force microscopy shows signs of degradation of the sample annealed at 600 °C. Electrical measurements indicate that the elevated annealing temperature results in an increase of the oxide depletion and the deep depletion capacitances simultaneously, that results in a reduction of the flat band voltage to zero, which is explained by fixed oxide charges curing. A forward bias step stress capacitance measurement shows that the total number of induced trapped charges are not strongly affected by the elevated annealing temperatures. Interface trap density of states analysis shows the lowest trapping concentration for the capacitor annealed at 500 °C. Above this temperature, the interface trap density of states increases. When all results are taken into consideration, we have found that the process thermal budget allows for an overlap between the gate oxide post metallization annealing and the ohmic contact formation at 500 °C.