Search Results
Time resolution and power consumption of a monolithic silicon pixel prototype in SiGe BiCMOS technology
2020, Paolozzi, L., Cardarelli, R., Débieux, S., Favre, Y., Ferrère, D., Gonzalez-Sevilla, S., Iacobucci, G., Kaynak, M., Martinelli, F., Nessi, M., Rücker, H., Sanna, I., Sultan, D.M.S., Valerio, P., Zaffaroni, E.
SiGe BiCMOS technology can be used to produce ultra-fast, low-power silicon pixel sensors that provide state-of-the-art time resolution even without internal gain. The development of such sensors requires the identification and control of the main factors that may degrade the timing performance as well as the characterisation of the dependance of the sensor time resolution on the amplifier power consumption. Measurements with a 90Sr source of a prototype sensor produced in SG13G2 technology from IHP Microelectronics shows a time resolution of 140 ps at an amplifier current of 7 µA and 45 ps at a power consumption of 150 µA. The resolution on the measurement of the signal time-over-threshold, which is used to correct for time walk, is the main factor affecting the timing performance of this prototype. c 2020 CERN. Published by IOP Publishing Ltd on behalf of Sissa Medialab.
A monolithic ASIC demonstrator for the Thin Time-of-Flight PET scanner
2019, Valerio, P., Cardarelli, R., Iacobucci, G., Paolozzi, L., Ripiccini, E., Hayakawa, D., Bruno, S., Caltabiano, A., Kaynak, M., Rücker, H., Nessi, M.
Time-of-flight measurement is an important advancement in PET scanners to improve image reconstruction with a lower delivered radiation dose. This article describes the monolithic ASIC for the TT-PET project, a novel idea for a high-precision PET scanner for small animals. The chip uses a SiGe Bi-CMOS process for timing measurements, integrating a fully-depleted pixel matrix with a low-power BJT-based front-end per channel, integrated on the same 100 µm thick die. The target timing resolution of the scanner is 30 ps RMS for electrons from the conversion of 511 keV photons. The system will include 1.6 million channels across almost 2000 different chips. A full-featured demonstrator chip with a 3×10 matrix of 500×500 µm2 pixels was fabricated to validate each block. Its design and experimental results are presented here. © 2019 CERN.