Filters

2014 - 201912020 - 20222

More filters

2019 - 201912020 - 20232
Reset filters

Settings

Author: Hilt, Oliver ×

Search Results

Now showing 1 - 3 of 3
  • Thumbnail Image
    Item
    On the Conduction Properties of Vertical GaN n-Channel Trench MISFETs
    ([New York, NY] : IEEE, 2021) Treidel, Eldad Bahat; Hilt, Oliver; Hoffmann, Veit; Brunner, Frank; Bickel, Nicole; Thies, Andreas; Tetzner, Kornelius; Gargouri, Hassan; Huber, Christian; Donimirski, Konstanty; Wurfl, Joachim
    ON-state conductance properties of vertical GaN n -channel trench MISFETs manufactured on different GaN substrates and having different gate trench orientations are studied up to 200 °C ambient temperature. The best performing devices, with a maximum output current above 4 kA/cm 2 and an area specific ON-state resistance of 1.1 mΩ·cm 2 , are manufactured on ammonothermal GaN substrate with the gate channel parallel to the a-plane of the GaN crystal. The scalability of the devices up to 40 mm gate periphery is investigated and demonstrated. It is found that, in addition to oxide interface traps, the semiconductor border traps in the p-GaN layer limit the available mobile channel electrons and that the channel surface roughness scattering limits the channel mobility. Both strongly depend on the gate trench orientation and on the GaN substrate defect density.
  • Thumbnail Image
    Item
    GaN Dioden und selbstsperrende GaN Schalttransistoren für effiziente Leistungswandler (GaN Powerswitch) : Verbundprojekt Leistungswandler in GaN-Technologie zur Erschließung ungenutzter Energiepotentiale (PowerGaNPlus) ; im BMBF Verbundvorhaben Leistungselektronik zur Energieeffizienz-Steigerung (LES) ; Laufzeit des Vorhabens: 1.06.2010 bis 31.05.2013
    (Hannover : Technische Informationsbibliothek (TIB), 2014) Hilt, Oliver
    Es wurden GaN-basierte laterale Dioden mit geringer Einsatzspannung und intrinsisch selbstsperrende Transistoren für den Einsatz in Schaltkonvertern realisiert. Transisorergebnisse: - Basierend auf dem p-GaN-Gate Modul wurden selbstsperrende 100 m / 600 V Transistoren mit 1 V Einsatzspannung realisiert. - Durch den Einsatz eines eisendotierten GaN-Puffers konnte die Erhöhung des dynamischen Einschaltwiderstands für das 250 V Schalten auf den Faktor 2.6 reduziert werden. - Die Schaltverluste sind kleiner als für Si-basierte Superjunction MOSFETs. Diodenergebnisse: - Durch die Entwicklung des zurückgesetzten Anodenkontaktes konnten 300 m / 600 V Dioden mit 0.5 V Einsatzspannung realisiert werden. - Die Schaltverluste sind so klein wie bei SiC-basierten HV-Schottkydioden. - Die Dioden wurden erfolgreich im Boost-Konverter (Systemdemonstrator) der Uni Erlangen eingesetzt.
  • Thumbnail Image
    Item
    Effects of post metallization annealing on Al2O3 atomic layer deposition on n-GaN
    (Bristol : IOP Publ., 2022) Tadmor, Liad; Brusaterra, Enrico; Treidel, Eldad Bahat; Brunner, Frank; Bickel, Nicole; Vandenbroucke, Sofie S. T.; Detavernier, Christophe; Würfl, Joachim; Hilt, Oliver
    The chemical, physical and electrical properties and the robustness of post metallization annealed Al2O3 atomic layers deposited on n-type GaN are investigated in this work. Planar metal insulator capacitors are used to demonstrate a gate-first with following ohmic contacts formation at elevated temperature up to 600 °C process flow. X-ray photoelectron spectroscopy indicates that no new bonds in the Al2O3 layer are formed due to exposure to the elevated annealing temperature. X-ray diffraction measurements show no crystallization of the oxide layer. Atomic force microscopy shows signs of degradation of the sample annealed at 600 °C. Electrical measurements indicate that the elevated annealing temperature results in an increase of the oxide depletion and the deep depletion capacitances simultaneously, that results in a reduction of the flat band voltage to zero, which is explained by fixed oxide charges curing. A forward bias step stress capacitance measurement shows that the total number of induced trapped charges are not strongly affected by the elevated annealing temperatures. Interface trap density of states analysis shows the lowest trapping concentration for the capacitor annealed at 500 °C. Above this temperature, the interface trap density of states increases. When all results are taken into consideration, we have found that the process thermal budget allows for an overlap between the gate oxide post metallization annealing and the ohmic contact formation at 500 °C.