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Author: Mahadevaiah, Mamathamba Kalishettyhalli × End date: 2024 × Start date: 2020 × End date: 2024 × Start date: 2020 × WGL Institute: IHP ×

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    Optimization of Multi-Level Operation in RRAM Arrays for In-Memory Computing
    (Basel : MDPI, 2021) Pérez, Eduardo; Pérez-Ávila, Antonio Javier; Romero-Zaliz, Rocío; Mahadevaiah, Mamathamba Kalishettyhalli; Pérez-Bosch Quesada, Emilio; Roldán, Juan Bautista; Jiménez-Molinos, Francisco; Wenger, Christian
    Accomplishing multi-level programming in resistive random access memory (RRAM) arrays with truly discrete and linearly spaced conductive levels is crucial in order to implement synaptic weights in hardware-based neuromorphic systems. In this paper, we implemented this feature on 4-kbit 1T1R RRAM arrays by tuning the programming parameters of the multi-level incremental step pulse with verify algorithm (M-ISPVA). The optimized set of parameters was assessed by comparing its results with a non-optimized one. The optimized set of parameters proved to be an effective way to define non-overlapped conductive levels due to the strong reduction of the device-to-device variability as well as of the cycle-to-cycle variability, assessed by inter-levels switching tests and during 1 k reset-set cycles. In order to evaluate this improvement in real scenarios, the experimental characteristics of the RRAM devices were captured by means of a behavioral model, which was used to simulate two different neuromorphic systems: an 8 × 8 vector-matrix-multiplication (VMM) accelerator and a 4-layer feedforward neural network for MNIST database recognition. The results clearly showed that the optimization of the programming parameters improved both the precision of VMM results as well as the recognition accuracy of the neural network in about 6% compared with the use of non-optimized parameters.
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    Analogue pattern recognition with stochastic switching binary CMOS-integrated memristive devices
    ([London] : Macmillan Publishers Limited, part of Springer Nature, 2020) Zahari, Finn; Pérez, Eduardo; Mahadevaiah, Mamathamba Kalishettyhalli; Kohlstedt, Hermann; Wenger, Christian; Ziegler, Martin
    Biological neural networks outperform current computer technology in terms of power consumption and computing speed while performing associative tasks, such as pattern recognition. The analogue and massive parallel in-memory computing in biology differs strongly from conventional transistor electronics that rely on the von Neumann architecture. Therefore, novel bio-inspired computing architectures have been attracting a lot of attention in the field of neuromorphic computing. Here, memristive devices, which serve as non-volatile resistive memory, are employed to emulate the plastic behaviour of biological synapses. In particular, CMOS integrated resistive random access memory (RRAM) devices are promising candidates to extend conventional CMOS technology to neuromorphic systems. However, dealing with the inherent stochasticity of resistive switching can be challenging for network performance. In this work, the probabilistic switching is exploited to emulate stochastic plasticity with fully CMOS integrated binary RRAM devices. Two different RRAM technologies with different device variabilities are investigated in detail, and their potential applications in stochastic artificial neural networks (StochANNs) capable of solving MNIST pattern recognition tasks is examined. A mixed-signal implementation with hardware synapses and software neurons combined with numerical simulations shows that the proposed concept of stochastic computing is able to process analogue data with binary memory cells. © 2020, The Author(s).