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- ItemAuthor Correction: Influence of plasma treatment on SiO2/Si and Si3N4/Si substrates for large-scale transfer of graphene([London] : Macmillan Publishers Limited, part of Springer Nature, 2021) Lukose, R.; Lisker, M.; Akhtar, F.; Fraschke, M.; Grabolla, T.; Mai, A.; Lukosius, M.The original version of this Article omitted an affiliation for M. Lisker. The correct affiliations for M. Lisker are listed below: IHP- Leibniz Institut für innovative Mikroelektronik, Im Technologiepark 25, 15236, Frankfurt (Oder), Germany Technical University of Applied Science Wildau, Hochschulring 1, 15745, Wildau, Germany The original Article and accompanying Supplementary Information file have been corrected.
- ItemInfluence of plasma treatment on SiO2/Si and Si3N4/Si substrates for large-scale transfer of graphene([London] : Macmillan Publishers Limited, part of Springer Nature, 2021) Lukose, R.; Lisker, M.; Akhtar, F.; Fraschke, M.; Grabolla, T.; Mai, A.; Lukosius, M.One of the limiting factors of graphene integration into electronic, photonic, or sensing devices is the unavailability of large-scale graphene directly grown on the isolators. Therefore, it is necessary to transfer graphene from the donor growth wafers onto the isolating target wafers. In the present research, graphene was transferred from the chemical vapor deposited 200 mm Germanium/Silicon (Ge/Si) wafers onto isolating (SiO2/Si and Si3N4/Si) wafers by electrochemical delamination procedure, employing poly(methylmethacrylate) as an intermediate support layer. In order to influence the adhesion properties of graphene, the wettability properties of the target substrates were investigated in this study. To increase the adhesion of the graphene on the isolating surfaces, they were pre-treated with oxygen plasma prior the transfer process of graphene. The wetting contact angle measurements revealed the increase of the hydrophilicity after surface interaction with oxygen plasma, leading to improved adhesion of the graphene on 200 mm target wafers and possible proof-of-concept development of graphene-based devices in standard Si technologies.
- ItemReliable metal-graphene contact formation process flows in a CMOS-compatible environment(Cambridge : Royal Society of Chemistry, 2022) Elviretti, M.; Lisker, M.; Lukose, R.; Lukosius, M.; Akhtar, F.; Mai, A.The possibility of exploiting the enormous potential of graphene for microelectronics and photonics must go through the optimization of the graphene-metal contact. Achieving low contact resistance is essential for the consideration of graphene as a candidate material for electronic and photonic devices. This work has been carried out in an 8′′ wafer pilot-line for the integration of graphene into a CMOS environment. The main focus is to study the impact of the patterning of graphene and passivation on metal-graphene contact resistance. The latter is measured by means of transmission line measurement (TLM) with several contact designs. The presented approaches enable reproducible formation of contact resistivity as low as 660 Ω μm with a sheet resistance of 1.8 kΩ/□ by proper graphene patterning, passivation of the channel and a post-processing treatment such as annealing.
- ItemLateral Selective SiGe Growth for Local Dislocation-Free SiGe-on-Insulator Virtual Substrate Fabrication(Pennington, NJ : ECS, 2023) Anand, K.; Schubert, M.A.; Corley-Wiciak, A.A.; Spirito, D.; Corley-Wiciak, C.; Klesse, W.M.; Mai, A.; Tillack, B.; Yamamoto, Y.Dislocation free local SiGe-on-insulator (SGOI) virtual substrate is fabricated using lateral selective SiGe growth by reduced pressure chemical vapor deposition. The lateral selective SiGe growth is performed around a ∼1.25 μm square Si (001) pillar in a cavity formed by HCl vapor phase etching of Si at 850 °C from side of SiO2/Si mesa structure on buried oxide. Smooth root mean square roughness of SiGe surface of 0.14 nm, which is determined by interface roughness between the sacrificially etched Si and the SiO2 cap, is obtained. Uniform Ge content of ∼40% in the laterally grown SiGe is observed. In the Si pillar, tensile strain of ∼0.65% is found which could be due to thermal expansion difference between SiO2 and Si. In the SiGe, tensile strain of ∼1.4% along 〈010〉 direction, which is higher compared to that along 〈110〉 direction, is observed. The tensile strain is induced from both [110] and [−110] directions. Threading dislocations in the SiGe are located only ∼400 nm from Si pillar and stacking faults are running towards 〈110〉 directions, resulting in the formation of a wide dislocation-free area in SiGe along 〈010〉 due to horizontal aspect ratio trapping.