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- ItemThe thermal stability of epitaxial GeSn layers(Melville, NY : AIP Publ., 2018) Zaumseil, P.; Hou, Y.; Schubert, M.A.; von den Driesch, N.; Stange, D.; Rainko, D.; Virgilio, M.; Buca, D.; Capellini, G.We report on the direct observation of lattice relaxation and Sn segregation of GeSn/Ge/Si heterostructures under annealing. We investigated strained and partially relaxed epi-layers with Sn content in the 5 at. %-12 at. % range. In relaxed samples, we observe a further strain relaxation followed by a sudden Sn segregation, resulting in the separation of a β-Sn phase. In pseudomorphic samples, a slower segregation process progressively leads to the accumulation of Sn at the surface only. The different behaviors are explained by the role of dislocations in the Sn diffusion process. The positive impact of annealing on optical emission is also discussed.
- ItemInvestigation of the copper gettering mechanism of oxide precipitates in silicon(Pennington, NJ : ECS, 2015) Kissinger, G.; Kot, D.; Klingsporn, M.; Schubert, M.A.; Sattler, A.; Müller, T.One of the reasons why the principal gettering mechanism of copper at oxide precipitates is not yet clarified is that it was not possible to identify the presence and measure the copper concentration in the vicinity of oxide precipitates. To overcome the problem we used a 14.5 nm thick thermal oxide layer as a model system for an oxide precipitate to localize the place where the copper is collected. We also analyzed a plate-like oxide precipitate by EDX and EELS and compared the results with the analysis carried out on the oxide layer. It is demonstrated that both the interface between the oxide precipitate being SiO2 and the silicon matrix and the interface between the thermal oxide and silicon consist of a 2–3 nm thick SiO layer. As the results of these experiments also show that copper segregates at the SiO interface layer of the thermal oxide it is concluded that gettering of copper by oxide precipitates is based on segregation of copper to the SiO interface layer.
- ItemLateral Selective SiGe Growth for Local Dislocation-Free SiGe-on-Insulator Virtual Substrate Fabrication(Pennington, NJ : ECS, 2023) Anand, K.; Schubert, M.A.; Corley-Wiciak, A.A.; Spirito, D.; Corley-Wiciak, C.; Klesse, W.M.; Mai, A.; Tillack, B.; Yamamoto, Y.Dislocation free local SiGe-on-insulator (SGOI) virtual substrate is fabricated using lateral selective SiGe growth by reduced pressure chemical vapor deposition. The lateral selective SiGe growth is performed around a ∼1.25 μm square Si (001) pillar in a cavity formed by HCl vapor phase etching of Si at 850 °C from side of SiO2/Si mesa structure on buried oxide. Smooth root mean square roughness of SiGe surface of 0.14 nm, which is determined by interface roughness between the sacrificially etched Si and the SiO2 cap, is obtained. Uniform Ge content of ∼40% in the laterally grown SiGe is observed. In the Si pillar, tensile strain of ∼0.65% is found which could be due to thermal expansion difference between SiO2 and Si. In the SiGe, tensile strain of ∼1.4% along 〈010〉 direction, which is higher compared to that along 〈110〉 direction, is observed. The tensile strain is induced from both [110] and [−110] directions. Threading dislocations in the SiGe are located only ∼400 nm from Si pillar and stacking faults are running towards 〈110〉 directions, resulting in the formation of a wide dislocation-free area in SiGe along 〈010〉 due to horizontal aspect ratio trapping.
- ItemDislocation generation and propagation during flash lamp annealing(Pennington, NJ : ECS, 2015) Kissinger, G.; Kot, D.; Schubert, M.A.; Sattler, A.Dislocation generation and propagation during flash lamp annealing for 20 ms was investigated using wafers with sawed, ground, and etched surfaces. Due to the thermal stress resulting from the temperature profiles generated by the flash pre-existing dislocations propagate into the wafer from both surfaces during flash lamp annealing. A dislocation free zone was observed around 700 μm depth below the surface of a 900 μm thick sawed wafer. The dislocation propagation can be well described by a three-dimensional mechanical model. It was further demonstrated that in wafers being initially free of dislocations no dislocations are generated during flash lamp annealing.
- ItemImpact of the precursor chemistry and process conditions on the cell-to-cell variability in 1T-1R based HfO2 RRAM devices(London : Nature Publishing Group, 2018) Grossi, A.; Perez, E.; Zambelli, C.; Olivo, P.; Miranda, E.; Roelofs, R.; Woodruff, J.; Raisanen, P.; Li, W.; Givens, M.; Costina, I.; Schubert, M.A.; Wenger, C.The Resistive RAM (RRAM) technology is currently in a level of maturity that calls for its integration into CMOS compatible memory arrays. This CMOS integration requires a perfect understanding of the cells performance and reliability in relation to the deposition processes used for their manufacturing. In this paper, the impact of the precursor chemistries and process conditions on the performance of HfO2 based memristive cells is studied. An extensive characterization of HfO2 based 1T1R cells, a comparison of the cell-to-cell variability, and reliability study is performed. The cells’ behaviors during forming, set, and reset operations are monitored in order to relate their features to conductive filament properties and process-induced variability of the switching parameters. The modeling of the high resistance state (HRS) is performed by applying the Quantum-Point Contact model to assess the link between the deposition condition and the precursor chemistry with the resulting physical cells characteristics.