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- ItemTowards the Growth of Hexagonal Boron Nitride on Ge(001)/Si Substrates by Chemical Vapor Deposition(Basel : MDPI, 2022) Franck, Max; Dabrowski, Jaroslaw; Schubert, Markus Andreas; Wenger, Christian; Lukosius, MindaugasThe growth of hexagonal boron nitride (hBN) on epitaxial Ge(001)/Si substrates via high-vacuum chemical vapor deposition from borazine is investigated for the first time in a systematic manner. The influences of the process pressure and growth temperature in the range of 10−7–10−3 mbar and 900–980 °C, respectively, are evaluated with respect to morphology, growth rate, and crystalline quality of the hBN films. At 900 °C, nanocrystalline hBN films with a lateral crystallite size of ~2–3 nm are obtained and confirmed by high-resolution transmission electron microscopy images. X-ray photoelectron spectroscopy confirms an atomic N:B ratio of 1 ± 0.1. A three-dimensional growth mode is observed by atomic force microscopy. Increasing the process pressure in the reactor mainly affects the growth rate, with only slight effects on crystalline quality and none on the principle growth mode. Growth of hBN at 980 °C increases the average crystallite size and leads to the formation of 3–10 well-oriented, vertically stacked layers of hBN on the Ge surface. Exploratory ab initio density functional theory simulations indicate that hBN edges are saturated by hydrogen, and it is proposed that partial de-saturation by H radicals produced on hot parts of the set-up is responsible for the growth.
- ItemVertical alignment control of self-ordered multilayered Ge nanodots on SiGe(Bristol : IOP Publ., 2023) Wen, Wei-Chen; Schubert, Markus Andreas; Tillack, Bernd; Yamamoto, YujiSelf-ordered multilayered Ge nanodots with SiGe spacers on a Si0.4Ge0.6 virtual substrate are fabricated using reduced-pressure chemical vapor deposition, and the mechanism of vertical ordering is investigated. The process conditions of Ge and SiGe layer deposition are H2-GeH4 at 550 °C and H2-SiH4-GeH4 at 500 °C-550 °C, respectively. By depositing the SiGe at 550 °C or increasing Ge content, the SiGe surface becomes smooth, resulting in vertically aligned Ge nanodots to reduce strain energy. Ge nanodots prefer to grow on the nanodot where the SiGe is relatively tensile strained due to the buried Ge nanodot underneath. By depositing at 500 °C and lowering Ge content, checkerboard-like surface forms, and the following Ge nanodots grow at staggered positions to reduce surface energy. The Ge nanodots are laterally aligned along the elastically soft 〈100〉 direction without pre-structuring resulting from the strain distribution.
- ItemModulating the Filamentary-Based Resistive Switching Properties of HfO2 Memristive Devices by Adding Al2O3 Layers(Basel : MDPI, 2022) Kalishettyhalli Mahadevaiah, Mamathamba; Perez, Eduardo; Lisker, Marco; Schubert, Markus Andreas; Perez-Bosch Quesada, Emilio; Wenger, Christian; Mai, AndreasThe resistive switching properties of HfO2 based 1T-1R memristive devices are electrically modified by adding ultra-thin layers of Al2 O3 into the memristive device. Three different types of memristive stacks are fabricated in the 130 nm CMOS technology of IHP. The switching properties of the memristive devices are discussed with respect to forming voltages, low resistance state and high resistance state characteristics and their variabilities. The experimental I–V characteristics of set and reset operations are evaluated by using the quantum point contact model. The properties of the conduction filament in the on and off states of the memristive devices are discussed with respect to the model parameters obtained from the QPC fit.
- ItemToward Reliable Compact Modeling of Multilevel 1T-1R RRAM Devices for Neuromorphic Systems(Basel : MDPI AG, 2021) Perez-Bosch Quesada, Emilio; Romero-Zaliz, Rocio; Perez, Eduardo; Kalishettyhalli Mahadevaiah, Mamathamba; Reuben, John; Schubert, Markus Andreas; Jimenez-Molinos, Francisco; Roldan, Juan Bautista; Wenger, ChristianIn this work, three different RRAM compact models implemented in Verilog-A are analyzed and evaluated in order to reproduce the multilevel approach based on the switching capability of experimental devices. These models are integrated in 1T-1R cells to control their analog behavior by means of the compliance current imposed by the NMOS select transistor. Four different resistance levels are simulated and assessed with experimental verification to account for their multilevel capability. Further, an Artificial Neural Network study is carried out to evaluate in a real scenario the viability of the multilevel approach under study.