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Vertical organic permeable dual-base transistors for logic circuits
The main advantage of organic transistors with dual gates/bases is that the threshold voltages can be set as a function of the applied second gate/base bias, which is crucial for the application in logic gates and integrated circuits. However, incorporating a dual gate/base structure into an ultra-short channel vertical architecture represents a substantial challenge. Here, we realize a device concept of vertical organic permeable dual-base transistors, where the dual base electrodes can be used to tune the threshold voltages and change the on-currents. The detailed operation mechanisms are investigated by calibrated TCAD simulations. Finally, power-efficient logic circuits, e.g. inverter, NAND/AND computation functions are demonstrated with one single device operating at supply voltages of <2.0 V. We believe that this work offers a compact and technologically simple hardware platform with excellent application potential for vertical-channel organic transistors in complex logic circuits.
Analysis of the Annealing Budget of Metal Oxide Thin-Film Transistors Prepared by an Aqueous Blade-Coating Process
Metal oxide (MO) semiconductors are widely used in electronic devices due to their high optical transmittance and promising electrical performance. This work describes the advancement toward an eco-friendly, streamlined method for preparing thin-film transistors (TFTs) via a pure water-solution blade-coating process with focus on a low thermal budget. Low temperature and rapid annealing of triple-coated indium oxide thin-film transistors (3C-TFTs) and indium oxide/zinc oxide/indium oxide thin-film transistors (IZI-TFTs) on a 300 nm SiO2 gate dielectric at 300 °C for only 60 s yields devices with an average field effect mobility of 10.7 and 13.8 cm2 V−1 s−1, respectively. The devices show an excellent on/off ratio (>106), and a threshold voltage close to 0 V when measured in air. Flexible MO-TFTs on polyimide substrates with AlOx dielectrics fabricated by rapid annealing treatment can achieve a remarkable mobility of over 10 cm2 V−1 s−1 at low operating voltage. When using a longer post-coating annealing period of 20 min, high-performance 3C-TFTs (over 18 cm2 V−1 s−1) and IZI-TFTs (over 38 cm2 V−1 s−1) using MO semiconductor layers annealed at 300 °C are achieved.