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- ItemBandwidth Improvement of MMIC Single-Pole-Double-Throw Passive HEMT Switches with Radial Stubs in Impedance-Transformation Networks(Basel : MDPI, 2020) Tsao, Yi-Fan; Würfl, Joachim; Hsu, Heng-TungIn this paper, we propose a new configuration for improving the isolation bandwidth of MMIC single-pole-double-throw (SPDT) passive high-electron-mobility transistor (HEMT) switches operating at millimeter frequency range. While the conventional configuration adopted open-stub loading for compensation of the off-state capacitance, radial stubs were introduced in our approach to improve the operational bandwidth of the SPDT switch. Implemented in 0.15 m GaAs pHEMT technology, the proposed configuration exhibited a measured insertion loss of less than 2.5 dB with better than 30 dB isolation level over the frequency range from 33 GHz to 44 GHz. In terms of the bandwidth of operation, the proposed configuration achieved a fractional bandwidth of 28.5% compared to that of 12.3% for the conventional approach. Such superior bandwidth performance is mainly attributed to the less frequency dependent nature of the radial stubs.
- ItemAnalysis of Mechanical Strain in AlGaN/GaN HFETs(Weinheim : Wiley-VCH, 2023) Yazdani, Hossein; Graff, Andreas; Simon-Najasek, Michél; Altmann, Frank; Brunner, Frank; Ostermay, Ina; Chevtchenko, Serguei; Würfl, JoachimHerein, the influence of mechanical strain induced by passivation layers on the electrical performance of AlGaN/GaN heterostructure field-effect transistor is investigated. We studied the physical mechanism of a threshold voltage (Vth) shift for the monolithically fabricated on/off devices reported earlier by our group. For that, theoretical calculations, simulation-based analysis, and nano-beam electron diffraction (NBED) measurements based on STEM are used. Strain distribution in the gate vicinity of transistors is compared for a SiNx passivation layer with intrinsic stress from ≈0.5 to −1 GPa for normally on and normally off devices, respectively. The strain in epitaxial layers transferred by intrinsic stress of SiNx is quantitatively evaluated using NEBD method. Strain dissimilarity Δε = 0.23% is detected between normally on and normally off devices. Using this method, quantitative correlation between 1.13 V of Vth shift and microscopic strain difference in the epitaxial layers caused by 1.5 GPa intrinsic stress variation in passivation layer is provided. It is showed in this correlation that about half of the reported threshold voltage shift is induced by strain, i.e., by the piezoelectric effect. The rest of Vth shift is caused by the fabrication process. Therefore, various components/mechanisms contributing to the measured Vth shift are distinguished.
- ItemEffects of post metallization annealing on Al2O3 atomic layer deposition on n-GaN(Bristol : IOP Publ., 2022) Tadmor, Liad; Brusaterra, Enrico; Treidel, Eldad Bahat; Brunner, Frank; Bickel, Nicole; Vandenbroucke, Sofie S. T.; Detavernier, Christophe; Würfl, Joachim; Hilt, OliverThe chemical, physical and electrical properties and the robustness of post metallization annealed Al2O3 atomic layers deposited on n-type GaN are investigated in this work. Planar metal insulator capacitors are used to demonstrate a gate-first with following ohmic contacts formation at elevated temperature up to 600 °C process flow. X-ray photoelectron spectroscopy indicates that no new bonds in the Al2O3 layer are formed due to exposure to the elevated annealing temperature. X-ray diffraction measurements show no crystallization of the oxide layer. Atomic force microscopy shows signs of degradation of the sample annealed at 600 °C. Electrical measurements indicate that the elevated annealing temperature results in an increase of the oxide depletion and the deep depletion capacitances simultaneously, that results in a reduction of the flat band voltage to zero, which is explained by fixed oxide charges curing. A forward bias step stress capacitance measurement shows that the total number of induced trapped charges are not strongly affected by the elevated annealing temperatures. Interface trap density of states analysis shows the lowest trapping concentration for the capacitor annealed at 500 °C. Above this temperature, the interface trap density of states increases. When all results are taken into consideration, we have found that the process thermal budget allows for an overlap between the gate oxide post metallization annealing and the ohmic contact formation at 500 °C.