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    On the Impact of Strained PECVD Nitride Layers on Oxide Precipitate Nucleation in Silicon
    (Pennington, NJ : ECS, 2019) Kissinger, G.; Kot, D.; Costina, I.; Lisker, M.
    PECVD nitride layers with different layer stress ranging from about 315 MPa to −1735 MPa were deposited on silicon wafers with similar concentration of interstitial oxygen. After a thermal treatment consisting of nucleation at 650°C for 4 h or 8 h followed annealing 780°C 3 h + 1000°C 16 h in nitrogen, the profiles of the oxide precipitate density were investigated. The binding states of hydrogen in the layers was investigated by FTIR. There is a clear effect of the layer stress on oxide precipitate nucleation. The higher the compressive layer stress is the higher is a BMD peak below the front surface. If the nitride layer is removed after the nucleation anneal the BMD peak below the front surface becomes lower. It is possible to model the BMD peak below the surface by vacancy in-diffusion from the silicon/nitride interface. With increasing duration of the nucleation anneal the vacancy injection from the silicon/nitride interface decreases and with increasing compressive layer stress it increases. © The Author(s) 2019.
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    Investigation of emitter homogeneity on laser doped emitters
    (Amsterdam [u.a.] : Elsevier, 2011) Germershausen, S.; Bartholomäus, L.; Seidel, U.; Hanisch, N.; Schieferdecker, A.; Küsters, K.H.; Kittler, M.; Ametowobla, M.; Einsele, F.; Dallmann, G.
    The selective emitter formation by laser doping is a well known process to increase the efficiency of silicon solar cells [1], [2]. For the characterization of laser doped emitters, SIMS (Secondary Ion Mass Spectroscopy) and ECV (Electrochemical Capacitance Voltage Measurement) techniques are used to analyze the emitter profile [3]. It is very difficult to get acceptable result by SIMS on a textured surface, so only ECV can be used. It has been shown, that a charge carrier depth profile can be measured on a homogeneous emitter only by ECV. The use of laser doping results in a non-homogeneous emitter. We have shown that the emitter depth is not just a function of the pulse power, but in addition of the surface structure of the wafer. The texture seems responsible for a strong variability in the doping profile. It has been shown, that the ECV measurement is not applicable to characterize the emitter depth on laser doped areas, because of the microscopic inhomogeneities in the emitter on the macroscopic measurement area. The real emitter profiles are to complex to be characterized by SIMS or ECV. We have shown that the variation in the emitter profile is resulting from the texture in the laser-doped regions.
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    On the Impact of Strained PECVD Oxide Layers on Oxide Precipitation in Silicon
    (Pennington, NJ : ECS, 2019) Kissinger, G.; Kot, D.; Lisker, M.; Sattler, A.
    PECVD oxide layers with different layer stress ranging from about −305.2 MPa to 39.9 MPa were deposited on silicon wafers with similar concentration of interstitial oxygen. After a thermal treatment consisting of rapid thermal annealing (RTA) and furnace annealing 780°C 3 h + 1000°C 16 h in nitrogen the profiles of the oxide precipitate density were investigated. Supersaturations of self-interstitials as function of layer stress were determined by adjusting modelling results to measured depth profiles of bulk microdefects. The self-interstitial supersaturation generated by RTA at 1250°C and 1175°C at the silicon/oxide interface is increasing linearly with increasing layer stress. Values for self-interstitial supersaturation determined on deposited oxide layers after RTA at 1250°C and 1175°C are very similar to values published for RTO by Sudo et al. An RTA at 1175°C with a PECVD oxide on top of the wafer is a method to effectively suppress oxygen precipitation in silicon wafers. Nucleation anneals carried out at 650°C for 4 h and 8 h did not show any effect of PECVD oxide layers on oxide precipitate nucleation. © The Author(s) 2019.
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    A graphene-based hot electron transistor
    (Washington, DC : American Chemical Society, 2013) Vaziri, S.; Lupina, G.; Henkel, C.; Smith, A.D.; Östling, M.; Dabrowski, J.; Lippert, G.; Mehr, W.; Lemme, M.C.
    We experimentally demonstrate DC functionality of graphene-based hot electron transistors, which we call graphene base transistors (GBT). The fabrication scheme is potentially compatible with silicon technology and can be carried out at the wafer scale with standard silicon technology. The state of the GBTs can be switched by a potential applied to the transistor base, which is made of graphene. Transfer characteristics of the GBTs show ON/OFF current ratios exceeding 104.