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End date: 2009 × Start date: 2000 × DDC: 530 × Has files: Yes × Type: Text × WGL Institute: IHP ×

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    Engineering the semiconductor/oxide interaction for stacking twin suppression in single crystalline epitaxial silicon(111)/insulator/Si(111) heterostructures
    (College Park, MD : Institute of Physics Publishing, 2008) Schroetter, T.; Zaumseil, P.; Seifarth, O.; Giussani, A.; Müssig, H.-J.; Storck, P.; Geiger, D.; Lichte, H.; Dabrowski, J.
    The integration of alternative semiconductor layers on the Si material platform via oxide heterostructures is of interest to increase the performance and/or functionality of future Si-based integrated circuits. The single crystalline quality of epitaxial (epi) semiconductor-insulator-Si heterostructures is however limited by too high defect densities, mainly due to a lack of knowledge about the fundamental physics of the heteroepitaxy mechanisms at work. To shed light on the physics of stacking twin formation as one of the major defect mechanisms in (111)-oriented fcc-related heterostructures on Si(111), we report a detailed experimental and theoretical study on the structure and defect properties of epi-Si(111)/Y2O 3/Pr2O3/Si(111) heterostructures. Synchrotron radiation-grazing incidence x-ray diffraction (SR-GIXRD) proves that the engineered Y2O3/Pr2O3 buffer dielectric heterostructure on Si(111) allows control of the stacking sequence of the overgrowing single crystalline epi-Si(111) layers. The epitaxy relationship of the epi-Si(111)/insulator/Si(111) heterostructure is characterized by a type A/B/A stacking configuration. Theoretical ab initio calculations show that this stacking sequence control of the heterostructure is mainly achieved by electrostatic interaction effects across the ionic oxide/covalent Si interface (IF). Transmission electron microscopy (TEM) studies detect only a small population of misaligned type B epi-Si(111) stacking twins whose location is limited to the oxide/epiSi IF region. Engineering the oxide/semiconductor IF physics by using tailored oxide systems opens thus a promising approach to grow heterostructures with well-controlled properties. © IOP Publishing Ltd and Deutsche Physikalische Gesellschaft.
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    An integrated 3.1-5.1 GHz pulse generator for ultra-wideband wireless localization systems
    (Göttingen : Copernicus, 2006) Fan, X.; Fischer, G.; Dietrich, B.
    This paper presents an implementation of an integrated Ultra-wideband (UWB), Binary-Phase Shift Keying (BPSK) Gaussian modulated pulse generator. VCO, multiplier and passive Gaussian filter are the key components. The VCO provides the carrier frequency of 4.1 GHz, the LC Gaussian filter is responsible for the pulse shaping in the baseband. Multiplying the baseband pulse and the VCO frequency shifts the pulse to the desired center frequency. The generated Gaussian pulse ocupppies the frequency range from 3.1 to 5.1 GHz with the center frequency at 4.1 GHz. Simulations and measured results show that this spectrum fulfills the mask for indoor communication systems given by the FCC (Federal Communications Commission, 2002). The total power consumption is 55 mW using a supply voltage of 2.5 V. Circuits are realized using the IHP 0.25 μm SiGe:C BiCMOS technology.
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    Phase noise and jitter modeling for fractional-N PLLs
    (Göttingen : Copernicus, 2007) Osmany, S.A.; Herzel, F.; Schmalz, K.; Winkler, W.
    We present an analytical phase noise model for fractional-N phase-locked loops (PLL) with emphasis on integrated RF synthesizers in the GHz range. The noise of the crystal reference, the voltage-controlled oscillator (VCO), the loop filter, the charge pump, and the sigma-delta modulator (SDM) is filtered by the PLL operation. We express the rms phase error (jitter) in terms of phase noise of the reference, the VCO phase noise and the third-order loop filter parameters. In addition, we consider OFDM systems, where the PLL phase noise is reduced by digital signal processing after down-conversion of the RF signal to baseband. The rms phase error is discussed as a function of the loop parameters. Our model drastically simplifies the noise optimization of the PLL loop dynamics.