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End date: 2024 × Start date: 2020 × DDC: 510 × WGL Institute: IHP ×

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    Methods increasing inherent resistance of ECC designs against horizontal attacks
    (Amsterdam [u.a.] : Elsevier Science, 2020) Kabin, Ievgen; Dyka, Zoya; Klann, Dan; Langendoerfer, Peter
    Due to the nature of applications such as critical infrastructure and the Internet of Things etc. side channel analysis attacks are becoming a serious threat. Side channel analysis attacks take advantage from the fact that the behaviour of crypto implementations can be observed and provides hints that simplify revealing keys. A new type of SCA is the so called horizontal differential SCA. In this paper we investigate two different approaches to increase the inherent resistance of our hardware accelerator for the kP operation. The first approach aims at reducing the impact of the addressing in our design by realizing a regular schedule of the addressing. In the second approach, we investigated how the formula used to implement the multiplication of GF(2n)-elements influences the results of horizontal DPA attacks against a Montgomery kP-implementation. We implemented 5 designs with different partial multipliers, i.e. based on different multiplication formulae. We used two different technologies, i.e. a 130 and a 250 nm technology, to simulate power traces for our analysis. We show that the implemented multiplication formula influences the success of horizontal attacks significantly. The combination of these two approaches leads to the most resistant design. For the 250 nm technology only 2 key candidates could be revealed with a correctness of about 70% which is a huge improvement given the fact that for the original design 7 key candidates achieved a correctness of more than 90%. For our 130 nm technology no key candidate was revealed with a correctness of more than 60%.
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    On the Complexity of Attacking Elliptic Curve Based Authentication Chips
    (Amsterdam [u.a.] : Elsevier, 2021) Kabin, Ievgen; Dyka, Zoya; Klann, Dan; Schaeffner, Jan; Langendoerfer, Peter
    In this paper we discuss the difficulties of mounting successful attacks against crypto implementations if essential information is missing. We start with a detailed description of our attack against our own design, to highlight which information is needed to increase the success of an attack, i.e. we use it as a blueprint to the following attack against commercially available crypto chips. We would like to stress that our attack against our own design is very similar to what happens during certification e.g. according to the Common Criteria Standard as in those cases the manufacturer needs to provide detailed information. If attacking commercial designs without signing NDAs, we were forced to intensively search the Internet for information about the designs. We were able to reveal information on the processing sequence during the authentication process even as detailed as identifying the clock cycles in which the individual key bits are processed. But we could not reveal the private keys used by the attacked commercial authentication chips 100% correctly. Moreover, as we did not knew the used keys we could not evaluate the success of our attack. To summarize, the effort of such an attack is significantly higher than the one of attacking a well-known implementation.
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    Time resolution and power consumption of a monolithic silicon pixel prototype in SiGe BiCMOS technology
    (London : Inst. of Physics, 2020) Paolozzi, L.; Cardarelli, R.; Débieux, S.; Favre, Y.; Ferrère, D.; Gonzalez-Sevilla, S.; Iacobucci, G.; Kaynak, M.; Martinelli, F.; Nessi, M.; Rücker, H.; Sanna, I.; Sultan, D.M.S.; Valerio, P.; Zaffaroni, E.
    SiGe BiCMOS technology can be used to produce ultra-fast, low-power silicon pixel sensors that provide state-of-the-art time resolution even without internal gain. The development of such sensors requires the identification and control of the main factors that may degrade the timing performance as well as the characterisation of the dependance of the sensor time resolution on the amplifier power consumption. Measurements with a 90Sr source of a prototype sensor produced in SG13G2 technology from IHP Microelectronics shows a time resolution of 140 ps at an amplifier current of 7 µA and 45 ps at a power consumption of 150 µA. The resolution on the measurement of the signal time-over-threshold, which is used to correct for time walk, is the main factor affecting the timing performance of this prototype. c 2020 CERN. Published by IOP Publishing Ltd on behalf of Sissa Medialab.