Filters

2020 - 20212

More filters

2021 - 20222
Reset filters

Settings

End date: 2024 × Start date: 2020 × DDC: 530 × Publisher: Basel : MDPI AG × WGL Institute: IHP ×

Search Results

Now showing 1 - 2 of 2
  • Thumbnail Image
    Item
    Programming Pulse Width Assessment for Reliable and Low-Energy Endurance Performance in Al:HfO2-Based RRAM Arrays
    (Basel : MDPI AG, 2020) Pérez, Eduardo; Ossorio, Óscar González; Dueñas, Salvador; Castán, Helena; García, Héctor; Wenger, Christian
    A crucial step in order to achieve fast and low-energy switching operations in resistive random access memory (RRAM) memories is the reduction of the programming pulse width. In this study, the incremental step pulse with verify algorithm (ISPVA) was implemented by using different pulse widths between 10 μ s and 50 ns and assessed on Al-doped HfO 2 4 kbit RRAM memory arrays. The switching stability was assessed by means of an endurance test of 1k cycles. Both conductive levels and voltages needed for switching showed a remarkable good behavior along 1k reset/set cycles regardless the programming pulse width implemented. Nevertheless, the distributions of voltages as well as the amount of energy required to carry out the switching operations were definitely affected by the value of the pulse width. In addition, the data retention was evaluated after the endurance analysis by annealing the RRAM devices at 150 °C along 100 h. Just an almost negligible increase on the rate of degradation of about 1 μ A at the end of the 100 h of annealing was reported between those samples programmed by employing a pulse width of 10 μ s and those employing 50 ns. Finally, an endurance performance of 200k cycles without any degradation was achieved on 128 RRAM devices by using programming pulses of 100 ns width.
  • Thumbnail Image
    Item
    Toward Reliable Compact Modeling of Multilevel 1T-1R RRAM Devices for Neuromorphic Systems
    (Basel : MDPI AG, 2021) Perez-Bosch Quesada, Emilio; Romero-Zaliz, Rocio; Perez, Eduardo; Kalishettyhalli Mahadevaiah, Mamathamba; Reuben, John; Schubert, Markus Andreas; Jimenez-Molinos, Francisco; Roldan, Juan Bautista; Wenger, Christian
    In this work, three different RRAM compact models implemented in Verilog-A are analyzed and evaluated in order to reproduce the multilevel approach based on the switching capability of experimental devices. These models are integrated in 1T-1R cells to control their analog behavior by means of the compliance current imposed by the NMOS select transistor. Four different resistance levels are simulated and assessed with experimental verification to account for their multilevel capability. Further, an Artificial Neural Network study is carried out to evaluate in a real scenario the viability of the multilevel approach under study.