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- ItemEditors' Choice - Precipitation of Suboxides in Silicon, their Role in Gettering of Copper Impurities and Carrier Recombination(Pennington, NJ : ECS, 2020) Kissinger, G.; Kot, D.; Huber, A.; Kretschmer, R.; Müller, T.; Sattler, A.This paper describes a theoretical investigation of the phase composition of oxide precipitates and the corresponding emission of self-interstitials at the minimum of the free energy and their evolution with increasing number of oxygen atoms in the precipitates. The results can explain the compositional evolution of oxide precipitates and the role of self-interstitials therein. The formation of suboxides at the edges of SiO2 precipitates after reaching a critical size can explain several phenomena like gettering of Cu by segregation to the suboxide region and lifetime reduction by recombination of minority carriers in the suboxide. It provides an alternative explanation, based on minimized free energy, to the theory of strained and unstrained plates. A second emphasis was payed to the evolution of the morphology of oxide precipitates. Based on the comparison with results from scanning transmission electron microscopy the sequence of morphology evolution of oxide precipitates was deduced. It turned out that it is opposite to the sequence assumed until now. © 2020 The Author(s). Published on behalf of The Electrochemical Society by IOP Publishing Limited.
- ItemLateral Selective SiGe Growth for Local Dislocation-Free SiGe-on-Insulator Virtual Substrate Fabrication(Pennington, NJ : ECS, 2023) Anand, K.; Schubert, M.A.; Corley-Wiciak, A.A.; Spirito, D.; Corley-Wiciak, C.; Klesse, W.M.; Mai, A.; Tillack, B.; Yamamoto, Y.Dislocation free local SiGe-on-insulator (SGOI) virtual substrate is fabricated using lateral selective SiGe growth by reduced pressure chemical vapor deposition. The lateral selective SiGe growth is performed around a ∼1.25 μm square Si (001) pillar in a cavity formed by HCl vapor phase etching of Si at 850 °C from side of SiO2/Si mesa structure on buried oxide. Smooth root mean square roughness of SiGe surface of 0.14 nm, which is determined by interface roughness between the sacrificially etched Si and the SiO2 cap, is obtained. Uniform Ge content of ∼40% in the laterally grown SiGe is observed. In the Si pillar, tensile strain of ∼0.65% is found which could be due to thermal expansion difference between SiO2 and Si. In the SiGe, tensile strain of ∼1.4% along 〈010〉 direction, which is higher compared to that along 〈110〉 direction, is observed. The tensile strain is induced from both [110] and [−110] directions. Threading dislocations in the SiGe are located only ∼400 nm from Si pillar and stacking faults are running towards 〈110〉 directions, resulting in the formation of a wide dislocation-free area in SiGe along 〈010〉 due to horizontal aspect ratio trapping.