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- ItemNanoscale Mapping of the 3D Strain Tensor in a Germanium Quantum Well Hosting a Functional Spin Qubit Device(Washington, DC : Soc., 2023) Corley-Wiciak, Cedric; Richter, Carsten; Zoellner, Marvin H.; Zaitsev, Ignatii; Manganelli, Costanza L.; Zatterin, Edoardo; Schülli, Tobias U.; Corley-Wiciak, Agnieszka A.; Katzer, Jens; Reichmann, Felix; Klesse, Wolfgang M.; Hendrickx, Nico W.; Sammak, Amir; Veldhorst, Menno; Scappucci, Giordano; Virgilio, Michele; Capellini, GiovanniA strained Ge quantum well, grown on a SiGe/Si virtual substrate and hosting two electrostatically defined hole spin qubits, is nondestructively investigated by synchrotron-based scanning X-ray diffraction microscopy to determine all its Bravais lattice parameters. This allows rendering the three-dimensional spatial dependence of the six strain tensor components with a lateral resolution of approximately 50 nm. Two different spatial scales governing the strain field fluctuations in proximity of the qubits are observed at <100 nm and >1 μm, respectively. The short-ranged fluctuations have a typical bandwidth of 2 × 10-4 and can be quantitatively linked to the compressive stressing action of the metal electrodes defining the qubits. By finite element mechanical simulations, it is estimated that this strain fluctuation is increased up to 6 × 10-4 at cryogenic temperature. The longer-ranged fluctuations are of the 10-3 order and are associated with misfit dislocations in the plastically relaxed virtual substrate. From this, energy variations of the light and heavy-hole energy maxima of the order of several 100 μeV and 1 meV are calculated for electrodes and dislocations, respectively. These insights over material-related inhomogeneities may feed into further modeling for optimization and design of large-scale quantum processors manufactured using the mainstream Si-based microelectronics technology.
- ItemElectron Transport across Vertical Silicon/MoS2/Graphene Heterostructures: Towards Efficient Emitter Diodes for Graphene Base Hot Electron Transistors(Washington, DC : ACS Publications, 2020) Belete, Melkamu; Engström, Olof; Vaziri, Sam; Lippert, Gunther; Lukosius, Mindaugas; Kataria, Satender; Lemme, Max C.Heterostructures comprising silicon, molybdenum disulfide (MoS2), and graphene are investigated with respect to the vertical current conduction mechanism. The measured current-voltage (I-V) characteristics exhibit temperature-dependent asymmetric current, indicating thermally activated charge carrier transport. The data are compared and fitted to a current transport model that confirms thermionic emission as the responsible transport mechanism across devices. Theoretical calculations in combination with the experimental data suggest that the heterojunction barrier from Si to MoS2 is linearly temperature-dependent for T = 200-300 K with a positive temperature coefficient. The temperature dependence may be attributed to a change in band gap difference between Si and MoS2, strain at the Si/MoS2 interface, or different electron effective masses in Si and MoS2, leading to a possible entropy change stemming from variation in density of states as electrons move from Si to MoS2. The low barrier formed between Si and MoS2 and the resultant thermionic emission demonstrated here make the present devices potential candidates as the emitter diode of graphene base hot electron transistors for future high-speed electronics. Copyright © 2020 American Chemical Society.
- ItemSelective electrodeposition of indium microstructures on silicon and their conversion into InAs and InSb semiconductors(New York, NY [u.a.] : Springer, 2023) Hnida-Gut, Katarzyna E.; Sousa, Marilyne; Tiwari, Preksha; Schmid, HeinzAbstract: The idea of benefitting from the properties of III-V semiconductors and silicon on the same substrate has been occupying the minds of scientists for several years. Although the principle of III-V integration on a silicon-based platform is simple, it is often challenging to perform due to demanding requirements for sample preparation rising from a mismatch in physical properties between those semiconductor groups (e.g. different lattice constants and thermal expansion coefficients), high cost of device-grade materials formation and their post-processing. In this paper, we demonstrate the deposition of group-III metal and III-V semiconductors in microfabricated template structures on silicon as a strategy for heterogeneous device integration on Si. The metal (indium) is selectively electrodeposited in a 2-electrode galvanostatic configuration with the working electrode (WE) located in each template, resulting in well-defined In structures of high purity. The semiconductors InAs and InSb are obtained by vapour phase diffusion of the corresponding group-V element (As, Sb) into the liquified In confined in the template. We discuss in detail the morphological and structural characterization of the synthesized In, InAs and InSb crystals as well as chemical analysis through scanning electron microscopy (SEM), scanning transmission electron microscopy (TEM/STEM), and energy-dispersive X-ray spectroscopy (EDX). The proposed integration path combines the advantage of the mature top-down lithography technology to define device geometries and employs economic electrodeposition (ED) and vapour phase processes to directly integrate difficult-to-process materials on a silicon platform. Graphical abstract: [Figure not available: see fulltext.].