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DDC: 620 × Subject: Transistors ×

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Now showing 1 - 3 of 3
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    Bilayer insulator tunnel barriers for graphene-based vertical hot-electron transistors
    (Cambridge : Royal Society of Chemistry, 2015) Vaziri, S.; Belete, M.; Dentoni Litta, E.; Smith, A.D.; Lupina, G.; Lemme, M.C.; Östling, M.
    Vertical graphene-based device concepts that rely on quantum mechanical tunneling are intensely being discussed in the literature for applications in electronics and optoelectronics. In this work, the carrier transport mechanisms in semiconductor–insulator–graphene (SIG) capacitors are investigated with respect to their suitability as electron emitters in vertical graphene base transistors (GBTs). Several dielectric materials as tunnel barriers are compared, including dielectric double layers. Using bilayer dielectrics, we experimentally demonstrate significant improvements in the electron injection current by promoting Fowler–Nordheim tunneling (FNT) and step tunneling (ST) while suppressing defect mediated carrier transport. High injected tunneling current densities approaching 103 A cm−2 (limited by series resistance), and excellent current–voltage nonlinearity and asymmetry are achieved using a 1 nm thick high quality dielectric, thulium silicate (TmSiO), as the first insulator layer, and titanium dioxide (TiO2) as a high electron affinity second layer insulator. We also confirm the feasibility and effectiveness of our approach in a full GBT structure which shows dramatic improvement in the collector on-state current density with respect to the previously reported GBTs. The device design and the fabrication scheme have been selected with future CMOS process compatibility in mind. This work proposes a bilayer tunnel barrier approach as a promising candidate to be used in high performance vertical graphene-based tunneling devices.
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    Integrated sensitive on-chip ion field effect transistors based on wrinkled ingaas nanomembranes
    (New York, NY [u.a.] : Springer, 2011) Harazim, S.M.; Feng, P.; Sanchez, S.; Deneke, C.; Mei, Y.; Schmidt, O.G.
    Self-organized wrinkling of pre-strained nanomembranes into nanochannels is used to fabricate a fully integrated nanofluidic device for the development of ion field effect transistors (IFETs). Constrained by the structure and shape of the membrane, the deterministic wrinkling process leads to a versatile variation of channel types such as straight two-way channels, three-way branched channels, or even four-way intersection channels. The fabrication of straight channels is well controllable and offers the opportunity to integrate multiple IFET devices into a single chip. Thus, several IFETs are fabricated on a single chip using a III-V semiconductor substrate to control the ion separation and to measure the ion current of a diluted potassium chloride electrolyte solution.
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    Design and Evaluation of Radiation-Hardened Standard Cell Flip-Flops
    (New York, NY : Institute of Electrical and Electronics Engineers, 2021) Schrape, Oliver; Andjelkovic, Marko; Breitenreiter, Anselm; Zeidler, Steffen; Balashov, Alexey; Krstic, Milos
    Use of a standard non-rad-hard digital cell library in the rad-hard design can be a cost-effective solution for space applications. In this paper we demonstrate how a standard non-rad-hard flip-flop, as one of the most vulnerable digital cells, can be converted into a rad-hard flip-flop without modifying its internal structure. We present five variants of a Triple Modular Redundancy (TMR) flip-flop: baseline TMR flip-flop, latch-based TMR flip-flop, True-Single Phase Clock (TSPC) TMR flip-flop, scannable TMR flip-flop and self-correcting TMR flip-flop. For all variants, the multi-bit upsets have been addressed by applying special placement constraints, while the Single Event Transient (SET) mitigation was achieved through the usage of customized SET filters and selection of optimal inverter sizes for the clock and reset trees. The proposed flip-flop variants feature differing performance, thus enabling to choose the optimal solution for every sensitive node in the circuit, according to the predefined design constraints. Several flip-flop designs have been validated on IHP’s 130nm BiCMOS process, by irradiation of custom-designed shift registers. It has been shown that the proposed TMR flip-flops are robust to soft errors with a threshold Linear Energy Transfer (LET) from ( 32.4 (MeV⋅cm2/mg) ) to ( 62.5 (MeV⋅cm2/mg) ), depending on the variant.