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Type: Text × Subject: Radiation hardening (electronics) ×

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    Design and Evaluation of Radiation-Hardened Standard Cell Flip-Flops
    (New York, NY : Institute of Electrical and Electronics Engineers, 2021) Schrape, Oliver; Andjelkovic, Marko; Breitenreiter, Anselm; Zeidler, Steffen; Balashov, Alexey; Krstic, Milos
    Use of a standard non-rad-hard digital cell library in the rad-hard design can be a cost-effective solution for space applications. In this paper we demonstrate how a standard non-rad-hard flip-flop, as one of the most vulnerable digital cells, can be converted into a rad-hard flip-flop without modifying its internal structure. We present five variants of a Triple Modular Redundancy (TMR) flip-flop: baseline TMR flip-flop, latch-based TMR flip-flop, True-Single Phase Clock (TSPC) TMR flip-flop, scannable TMR flip-flop and self-correcting TMR flip-flop. For all variants, the multi-bit upsets have been addressed by applying special placement constraints, while the Single Event Transient (SET) mitigation was achieved through the usage of customized SET filters and selection of optimal inverter sizes for the clock and reset trees. The proposed flip-flop variants feature differing performance, thus enabling to choose the optimal solution for every sensitive node in the circuit, according to the predefined design constraints. Several flip-flop designs have been validated on IHP’s 130nm BiCMOS process, by irradiation of custom-designed shift registers. It has been shown that the proposed TMR flip-flops are robust to soft errors with a threshold Linear Energy Transfer (LET) from ( 32.4 (MeV⋅cm2/mg) ) to ( 62.5 (MeV⋅cm2/mg) ), depending on the variant.
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    JICG CMOS transistors for reduction of total ionizing dose and single event effects in a 130 nm bulk SiGe BiCMOS technology
    (Amsterdam : North-Holland Publ. Co., 2020) Sorge, R.; Schmidt, J.; Wipf, Ch.; Reimer, F.; Teply, F.; Korndörfer, F.
    We report on a novel radiation hardening by design (RHBD) approach for mitigation of total ionization dose (TID) induced drain leakage currents and single event transient (SET) in digital circuits fabricated in a 130 nm bulk SiGe BiCMOS technology. In order to avoid significant TID induced increase of drain leakage currents for NMOS transistors and channel pinch-off for PMOS transistors due to positive charges trapped at the lateral shallow trench insulator silicon interface we introduced junction isolation (JI) for the lateral MOS channel regions. The device construction measures applied also support to suppress the generation SETs. The tolerance of JI MOS transistors against TID induced drain leakage currents was verified up to a TID > 1.3 Mrad(Si). SET tests performed at four different inverter types varying in the arrangement the deep well in the layout. For CMOS inverters with isolated NMOS transistors a LET threshold > 130 MeV cm2 mg−1 was obtained.