Filters

2010 - 20172

More filters

2019 - 201912020 - 20231
Reset filters

Settings

Publisher: London : Hindawi × Subject: State of the art ×

Search Results

Now showing 1 - 2 of 2
  • Thumbnail Image
    Item
    Adaptable security in wireless sensor networks by using reconfigurable ECC hardware coprocessors
    (London : Hindawi, 2010) Portilla, J.; Otero, A.; de la Torre, E.; Riesgo, T.; Stecklina, O.; Peter, S.; Langendörfer, P.
    Specific features of Wireless Sensor Networks (WSNs) like the open accessibility to nodes, or the easy observability of radio communications, lead to severe security challenges. The application of traditional security schemes on sensor nodes is limited due to the restricted computation capability, low-power availability, and the inherent low data rate. In order to avoid dependencies on a compromised level of security, a WSN node with a microcontroller and a Field Programmable Gate Array (FPGA) is used along this work to implement a state-of-the art solution based on ECC (Elliptic Curve Cryptography). In this paper it is described how the reconfiguration possibilities of the system can be used to adapt ECC parameters in order to increase or reduce the security level depending on the application scenario or the energy budget. Two setups have been created to compare the softwareand hardware-supported approaches. According to the results, the FPGA-based ECC implementation requires three orders of magnitude less energy, compared with a low power microcontroller implementation, even considering the power consumption overhead introduced by the hardware reconfiguration.
  • Thumbnail Image
    Item
    Data link layer considerations for future 100 Gbps terahertz band transceivers
    (London : Hindawi, 2017) Lopacinski, Lukasz; Brzozowski, Marcin; Kraemer, Rolf
    This paper presents a hardware processor for 100Gbps wireless data link layer. A serial Reed-Solomon decoder requires a clock of 12.5GHz to fulfill timings constraints of the transmission. Receiving a single Ethernet frame on a 100 Gbps physical layer may be faster than accessing DDR3 memory. Processing so fast streams on a state-of-the-art FPGA (field programmable gate arrays) requires a dedicated approach. Thus, the paper presents lightweight RS FEC engine, frames fragmentation, aggregation, and a protocol with selective fragment retransmission. The implemented FPGA demonstrator achieves nearly 120 Gbps and accepts bit error rate (BER) up to 2e - 3. Moreover, redundancy added to the frames is adopted according to the channel BER by a dedicated link adaptation algorithm. At the end, ASIC synthesis results are presented including detailed statistics of consumed energy per bit.