Charge pump design in 130 nm SiGe BiCMOS technology for low-noise fractional-N PLLs

Abstract

This paper presents a numerical comparison of charge pumps (CP) designed for a high linearity and a low noise to be used in a fractional-N phase-locked loop (PLL). We consider a PLL architecture, where two parallel CPs with DC offset are used. The CP for VCO fine tuning is biased at the output to keep the VCO gain constant. For this specific architecture, only one transistor per CP is relevant for phase detector linearity. This can be an nMOSFET, a pMOSFET or a SiGe HBT, depending on the design. The HBT-based CP shows the highest linearity, whereas all charge pumps show similar device noise. An internal supply regulator with low intrinsic device noise is included in the design optimization.