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Author: Herzel, F. ×

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Now showing 1 - 4 of 4
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    An X-Band low-power and low-phase-noise VCO using bondwire inductor
    (München : European Geopyhsical Union, 2009) Hu, K.; Herzel, F.; Scheytt, J.C.
    In this paper a low-power low-phase-noise voltage-controlled-oscillator (VCO) has been designed and, fabricated in 0.25 μm SiGe BiCMOS process. The resonator of the VCO is implemented with on-chip MIM capacitors and a single aluminum bondwire. A tail current filter is realized to suppress flicker noise up-conversion. The measured phase noise is −126.6 dBc/Hz at 1 MHz offset from a 7.8 GHz carrier. The figure of merit (FOM) of the VCO is −192.5 dBc/Hz and the VCO core consumes 4 mA from a 3.3 V power supply. To the best of our knowledge, this is the best FOM and the lowest phase noise for bondwire VCOs in the X-band. This VCO will be used for satellite communications.
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    Charge pump design in 130 nm SiGe BiCMOS technology for low-noise fractional-N PLLs
    (München : European Geopyhsical Union, 2015) Kucharski, M.; Herzel, F.
    This paper presents a numerical comparison of charge pumps (CP) designed for a high linearity and a low noise to be used in a fractional-N phase-locked loop (PLL). We consider a PLL architecture, where two parallel CPs with DC offset are used. The CP for VCO fine tuning is biased at the output to keep the VCO gain constant. For this specific architecture, only one transistor per CP is relevant for phase detector linearity. This can be an nMOSFET, a pMOSFET or a SiGe HBT, depending on the design. The HBT-based CP shows the highest linearity, whereas all charge pumps show similar device noise. An internal supply regulator with low intrinsic device noise is included in the design optimization.
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    Self-calibrating highly sensitive dynamic capacitance sensor: Towards rapid sensing and counting of particles in laminar flow systems
    (Cambridge : Royal Society of Chemistry, 2015) Guha, S.; Schmalz, K.; Wenger, Ch.; Herzel, F.
    In this report we propose a sensor architecture and a corresponding read-out technique on silicon for the detection of dynamic capacitance change. This approach can be applied to rapid particle counting and single particle sensing in a fluidic system. The sensing principle is based on capacitance variation of an interdigitated electrode (IDE) structure embedded in an oscillator circuit. The capacitance scaling of the IDE results in frequency modulation of the oscillator. A demodulator architecture is employed to provide a read-out of the frequency modulation caused by the capacitance change. A self-calibrating technique is employed at the read-out amplifier stage. The capacitance variation of the IDE due to particle flow causing frequency modulation and the corresponding demodulator read-out has been analytically modelled. Experimental verification of the established model and the functionality of the sensor chip were shown using a modulating capacitor independent of fluidic integration. The initial results show that the sensor is capable of detecting frequency changes of the order of 100 parts per million (PPM), which translates to a shift of 1.43 MHz at 14.3 GHz operating frequency. It is also shown that a capacitance change every 3 μs can be accurately detected.
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    Phase noise and jitter modeling for fractional-N PLLs
    (Göttingen : Copernicus, 2007) Osmany, S.A.; Herzel, F.; Schmalz, K.; Winkler, W.
    We present an analytical phase noise model for fractional-N phase-locked loops (PLL) with emphasis on integrated RF synthesizers in the GHz range. The noise of the crystal reference, the voltage-controlled oscillator (VCO), the loop filter, the charge pump, and the sigma-delta modulator (SDM) is filtered by the PLL operation. We express the rms phase error (jitter) in terms of phase noise of the reference, the VCO phase noise and the third-order loop filter parameters. In addition, we consider OFDM systems, where the PLL phase noise is reduced by digital signal processing after down-conversion of the RF signal to baseband. The rms phase error is discussed as a function of the loop parameters. Our model drastically simplifies the noise optimization of the PLL loop dynamics.