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A survey on Bluetooth multi-hop networks
Bluetooth was firstly announced in 1998. Originally designed as cable replacement connecting devices in a point-to-point fashion its high penetration arouses interest in its ad-hoc networking potential. This ad-hoc networking potential of Bluetooth is advertised for years - but until recently no actual products were available and less than a handful of real Bluetooth multi-hop network deployments were reported. The turnaround was triggered by the release of the Bluetooth Low Energy Mesh Profile which is unquestionable a great achievement but not well suited for all use cases of multi-hop networks. This paper surveys the tremendous work done on Bluetooth multi-hop networks during the last 20 years. All aspects are discussed with demands for a real world Bluetooth multi-hop operation in mind. Relationships and side effects of different topics for a real world implementation are explained. This unique focus distinguishes this survey from existing ones. Furthermore, to the best of the authors’ knowledge this is the first survey consolidating the work on Bluetooth multi-hop networks for classic Bluetooth technology as well as for Bluetooth Low Energy. Another individual characteristic of this survey is a synopsis of real world Bluetooth multi-hop network deployment efforts. In fact, there are only four reports of a successful establishment of a Bluetooth multi-hop network with more than 30 nodes and only one of them was integrated in a real world application - namely a photovoltaic power plant. © 2019 The Authors
Analysis of Single Event Transient Effects in Standard Delay Cells Based on Decoupling Capacitors
Single Event Transients (SETs), i.e., voltage glitches induced in combinational logic as a result of the passage of energetic particles, represent an increasingly critical reliability threat for modern complementary metal oxide semiconductor (CMOS) integrated circuits (ICs) employed in space missions. In rad-hard ICs implemented with standard digital cells, special design techniques should be applied to reduce the Soft Error Rate (SER) due to SETs. To this end, it is essential to consider the SET robustness of individual standard cells. Among the wide range of logic cells available in standard cell libraries, the standard delay cells (SDCs) implemented with the skew-sized inverters are exceptionally vulnerable to SETs. Namely, the SET pulses induced in these cells may be hundreds of picoseconds longer than those in other standard cells. In this work, an alternative design of a SDC based on two inverters and two decoupling capacitors is introduced. Electrical simulations have shown that the propagation delay and SET robustness of the proposed delay cell are strongly influenced by the transistor sizes and supply voltage, while the impact of temperature is moderate. The proposed design is more tolerant to SETs than the SDCs with skew-sized inverters, and occupies less area compared to the hardening configurations based on partial and complete duplication. Due to the low transistor count (only six transistors), the proposed delay cell could also be used as a SET filter.
Kafka-ML: Connecting the data stream with ML/AI frameworks
Machine Learning (ML) and Artificial Intelligence (AI) depend on data sources to train, improve, and make predictions through their algorithms. With the digital revolution and current paradigms like the Internet of Things, this information is turning from static data to continuous data streams. However, most of the ML/AI frameworks used nowadays are not fully prepared for this revolution. In this paper, we propose Kafka-ML, a novel and open-source framework that enables the management of ML/AI pipelines through data streams. Kafka-ML provides an accessible and user-friendly Web user interface where users can easily define ML models, to then train, evaluate, and deploy them for inferences. Kafka-ML itself and the components it deploys are fully managed through containerization technologies, which ensure their portability, easy distribution, and other features such as fault-tolerance and high availability. Finally, a novel approach has been introduced to manage and reuse data streams, which may eliminate the need for data storage or file systems.
Dual-Band Transmitter and Receiver With Bowtie-Antenna in 0.13 μm SiGe BiCMOS for Gas Spectroscopy at 222 - 270 GHz
This paper presents a transmitter (TX) and a receiver (RX) with bowtie-antenna and silicon lens for gas spectroscopy at 222-270 GHz, which are fabricated in IHP's 0.13 μm SiGe BiCMOS technology. The TX and RX use two integrated local oscillators for 222 - 256 GHz and 250 - 270 GHz, which are switched for dual-band operation. Due to its directivity of about 27 dBi, the single integrated bowtie-antenna with silicon lens enables an EIRP of about 25 dBm for the TX, and therefore a considerably higher EIRP for the 2-band TX compared to previously reported systems. The double sideband noise temperature of the RX is 20,000 K (18.5 dB noise figure) as measured by the Y-factor method. Absorption spectroscopy of gaseous methanol is used as a measure for the performance of the gas spectroscopy system with TX- and RX-modules.
Artificial intelligence in marketing: friend or foe of sustainable consumption?
[No abstract available]
Resistance of the Montgomery Ladder Against Simple SCA: Theory and Practice
The Montgomery kP algorithm i.e. the Montgomery ladder is reported in literature as resistant against simple SCA due to the fact that the processing of each key bit value of the scalar k is done using the same sequence of operations. We implemented the Montgomery kP algorithm using Lopez-Dahab projective coordinates for the NIST elliptic curve B-233. We instantiated the same VHDL code for a wide range of clock frequencies for the same target FPGA and using the same compiler options. We measured electromagnetic traces of the kP executions using the same input data, i.e. scalar k and elliptic curve point P, and measurement setup. Additionally, we synthesized the same VHDL code for two IHP CMOS technologies, for a broad spectrum of frequencies. We simulated the power consumption of each synthesized design during an execution of the kP operation, always using the same scalar k and elliptic curve point P as inputs. Our experiments clearly show that the success of simple electromagnetic analysis attacks against FPGA implementations as well as the one of simple power analysis attacks against synthesized ASIC designs depends on the target frequency for which the design was implemented and at which it is executed significantly. In our experiments the scalar k was successfully revealed via simple visual inspection of the electromagnetic traces of the FPGA for frequencies from 40 to 100 MHz when standard compile options were used as well as from 50 MHz up to 240 MHz when performance optimizing compile options were used. We obtained similar results attacking the power traces simulated for the ASIC. Despite the significant differences of the here investigated technologies the designs’ resistance against the attacks performed is similar: only a few points in the traces represent strong leakage sources allowing to reveal the key at very low and very high frequencies. For the “middle” frequencies the number of points which allow to successfully reveal the key increases when increasing the frequency.
Through the Window: Exploitation and Countermeasures of the ESP32 Register Window Overflow †
With the increasing popularity of IoT (Internet-of-Things) devices, their security becomes an increasingly important issue. Buffer overflow vulnerabilities have been known for decades, but are still relevant, especially for embedded devices where certain security measures cannot be implemented due to hardware restrictions or simply due to their impact on performance. Therefore, many buffer overflow detection mechanisms check for overflows only before critical data are used. All data that an attacker could use for his own purposes can be considered critical. It is, therefore, essential that all critical data are checked between writing a buffer and its usage. This paper presents a vulnerability of the ESP32 microcontroller, used in millions of IoT devices, that is based on a pointer that is not protected by classic buffer overflow detection mechanisms such as Stack Canaries or Shadow Stacks. This paper discusses the implications of vulnerability and presents mitigation techniques, including a patch, that fixes the vulnerability. The overhead of the patch is evaluated using simulation as well as an ESP32-WROVER-E development board. We showed that, in the simulation with 32 general-purpose registers, the overhead for the CoreMark benchmark ranges between 0.1% and 0.4%. On the ESP32, which uses an Xtensa LX6 core with 64 general-purpose registers, the overhead went down to below 0.01%. A worst-case scenario, modeled by a synthetic benchmark, showed overheads up to 9.68%.
GALS for Bursty Data Transfer based on Clock Coupling
In this paper we introduce a novel burst-mode GALS technique. The goal of this technique is improving the performance of the GALS approach for systems with predominantly bursty data transfer. This new technique has been used to implement a GALS-based version of a hardware accelerator of a 60 GHz OFDM baseband processor. The simulation results show a significant performance improvement in comparison with a classical implementation of GALS using pausible clocking. © 2009 Elsevier B.V. All rights reserved.
Resilience in the Cyberworld: Definitions, Features and Models
Resilience is a feature that is gaining more and more attention in computer science and computer engineering. However, the definition of resilience for the cyber landscape, especially embedded systems, is not yet clear. This paper discusses definitions provided by different authors, on different years and with different application areas the field of computer science/computer engineering. We identify the core statements that are more or less common to the majority of the definitions, and based on this we give a holistic definition using attributes for (cyber-) resilience. In order to pave a way towards resilience engineering, we discuss a theoretical model of the life cycle of a (cyber-) resilient system that consists of key actions presented in the literature. We adapt this model for embedded (cyber-) resilient systems.
Ridge Gap Waveguide Based Liquid Crystal Phase Shifter
In this paper, the gap waveguide technology is examined for packaging liquid crystal (LC) in tunable microwave devices. For this purpose, a line based passive phase shifter is designed and implemented in a ridge gap waveguide (RGW) topology and filled with LC serving as functional material. The inherent direct current (DC) decoupling property of gap waveguides is used to utilize the waveguide surroundings as biasing electrodes for tuning the LC. The bed of nails structure of the RGW exhibits an E-field suppression of 76 dB in simulation, forming a completely shielded device. The phase shifter shows a maximum figure of merit (FoM) of 70 °/dB from 20 GHz to 30 GHz with a differential phase shift of 387° at 25 GHz. The insertion loss ranges from 3.5 dB to 5.5 dB depending on the applied biasing voltage of 0 V to 60 V. © 2013 IEEE.