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Subject: State of the art × WGL Institute: IHP ×

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Now showing 1 - 4 of 4
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    Novel concept for VCSEL enhanced silicon photonic coherent transceiver
    (New York, NY : American Inst. of Physics, 2019) Seiler, Pascal M.; Ronniger, Gregor; Troppenz, Ute; Sigmund, Ariane; Moehrle, Martin; Peczek, Anna; Zimmermann, Lars
    We present a novel concept for an integrated silicon photonic coherent transceiver using vertical-emitting laser sources at 1550 nm. In a state of the art external modulation configuration, we deploy a VCSEL on the transmit and a HCSEL on the receive side. We demonstrate the feasibility of this approach by externally modulating the VCSEL with QPSK at up to 28 Gbaud. We also perform experiments with the VCSEL-HCSEL configuration in a slave-master optical injection locking setup for future data center interconnects. The results show stable locking conditions and the VCSEL is detuned to perform predominant phase modulation. To the best of our knowledge, this is the first time direct phase modulation of a VCSEL under optical injection locking was demonstrated using two vertically emitting laser sources as master - and slave laser. © 2019 Author(s).
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    Toward Reliable Multi-Level Operation in RRAM Arrays: Improving Post-Algorithm Stability and Assessing Endurance/Data Retention
    (Piscataway : Institute of Electrical and Electronics Engineers Inc., 2019) Perez, E.; Zambelli, C.; Mahadevaiah, M.K.; Olivo, P.; Wenger, C.
    Achieving a reliable multi-level operation in resistive random access memory (RRAM) arrays is currently a challenging task due to several threats like the post-algorithm instability occurring after the levels placement, the limited endurance, and the poor data retention capabilities at high temperature. In this paper, we introduced a multi-level variation of the state-of-the-art incremental step pulse with verify algorithm (M-ISPVA) to improve the stability of the low resistive state levels. This algorithm introduces for the first time the proper combination of current compliance control and program/verify paradigms. The validation of the algorithm for forming and set operations has been performed on 4-kbit RRAM arrays. In addition, we assessed the endurance and the high temperature multi-level retention capabilities after the algorithm application proving a 1 k switching cycles stability and a ten years retention target with temperatures below 100 °C.
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    Adaptable security in wireless sensor networks by using reconfigurable ECC hardware coprocessors
    (London : Hindawi, 2010) Portilla, J.; Otero, A.; de la Torre, E.; Riesgo, T.; Stecklina, O.; Peter, S.; Langendörfer, P.
    Specific features of Wireless Sensor Networks (WSNs) like the open accessibility to nodes, or the easy observability of radio communications, lead to severe security challenges. The application of traditional security schemes on sensor nodes is limited due to the restricted computation capability, low-power availability, and the inherent low data rate. In order to avoid dependencies on a compromised level of security, a WSN node with a microcontroller and a Field Programmable Gate Array (FPGA) is used along this work to implement a state-of-the art solution based on ECC (Elliptic Curve Cryptography). In this paper it is described how the reconfiguration possibilities of the system can be used to adapt ECC parameters in order to increase or reduce the security level depending on the application scenario or the energy budget. Two setups have been created to compare the softwareand hardware-supported approaches. According to the results, the FPGA-based ECC implementation requires three orders of magnitude less energy, compared with a low power microcontroller implementation, even considering the power consumption overhead introduced by the hardware reconfiguration.
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    Data link layer considerations for future 100 Gbps terahertz band transceivers
    (London : Hindawi, 2017) Lopacinski, Lukasz; Brzozowski, Marcin; Kraemer, Rolf
    This paper presents a hardware processor for 100Gbps wireless data link layer. A serial Reed-Solomon decoder requires a clock of 12.5GHz to fulfill timings constraints of the transmission. Receiving a single Ethernet frame on a 100 Gbps physical layer may be faster than accessing DDR3 memory. Processing so fast streams on a state-of-the-art FPGA (field programmable gate arrays) requires a dedicated approach. Thus, the paper presents lightweight RS FEC engine, frames fragmentation, aggregation, and a protocol with selective fragment retransmission. The implemented FPGA demonstrator achieves nearly 120 Gbps and accepts bit error rate (BER) up to 2e - 3. Moreover, redundancy added to the frames is adopted according to the channel BER by a dedicated link adaptation algorithm. At the end, ASIC synthesis results are presented including detailed statistics of consumed energy per bit.