GALS for Bursty Data Transfer based on Clock Coupling

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dc.bibliographicCitation.firstPage103eng
dc.bibliographicCitation.journalTitleElectronic Notes in Theoretical Computer Scienceeng
dc.bibliographicCitation.volume245eng
dc.contributor.authorKrstić, M.
dc.contributor.authorFan, X.
dc.contributor.authorGrass, E.
dc.contributor.authorGürkaynak, F.K.
dc.date.accessioned2020-08-12T05:34:49Z
dc.date.available2020-08-12T05:34:49Z
dc.date.issued2009
dc.description.abstractIn this paper we introduce a novel burst-mode GALS technique. The goal of this technique is improving the performance of the GALS approach for systems with predominantly bursty data transfer. This new technique has been used to implement a GALS-based version of a hardware accelerator of a 60 GHz OFDM baseband processor. The simulation results show a significant performance improvement in comparison with a classical implementation of GALS using pausible clocking. © 2009 Elsevier B.V. All rights reserved.eng
dc.description.versionpublishedVersioneng
dc.identifier.urihttps://doi.org/10.34657/4102
dc.identifier.urihttps://oa.tib.eu/renate/handle/123456789/5473
dc.language.isoengeng
dc.publisherAmsterdam : Elseviereng
dc.relation.doihttps://doi.org/10.1016/j.entcs.2009.07.031
dc.relation.issn1571-0661
dc.rights.licenseCC BY-NC-ND 3.0 Unportedeng
dc.rights.urihttps://creativecommons.org/licenses/by-nc-nd/3.0/eng
dc.subject.ddc004eng
dc.subject.otherbursty data transfereng
dc.subject.otherGALSeng
dc.subject.otherpausible clockingeng
dc.subject.otherBaseband processorseng
dc.subject.otherBurst-modeeng
dc.subject.otherbursty data transfereng
dc.subject.otherGALSeng
dc.subject.otherHardware acceleratorseng
dc.subject.otherpausible clockingeng
dc.subject.otherPerformance improvementseng
dc.subject.otherSimulation resulteng
dc.subject.otherData transfereng
dc.titleGALS for Bursty Data Transfer based on Clock Couplingeng
dc.typeArticleeng
dc.typeTexteng
tib.accessRightsopenAccesseng
wgl.contributorIHPeng
wgl.subjectInformatikeng
wgl.typeZeitschriftenartikeleng
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