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    Label free sensing of creatinine using a 6 GHz CMOS near-field dielectric immunosensor
    (Cambridge : Royal Society of Chemistry, 2015) Guha, S.; Warsinke, A.; Tientcheu, Ch.M.; Schmalz, K.; Meliani, C.; Wenger, Ch.
    In this work we present a CMOS high frequency direct immunosensor operating at 6 GHz (C-band) for label free determination of creatinine. The sensor is fabricated in standard 0.13 μm SiGe:C BiCMOS process. The report also demonstrates the ability to immobilize creatinine molecules on a Si3N4 passivation layer of the standard BiCMOS/CMOS process, therefore, evading any further need of cumbersome post processing of the fabricated sensor chip. The sensor is based on capacitive detection of the amount of non-creatinine bound antibodies binding to an immobilized creatinine layer on the passivated sensor. The chip bound antibody amount in turn corresponds indirectly to the creatinine concentration used in the incubation phase. The determination of creatinine in the concentration range of 0.88–880 μM is successfully demonstrated in this work. A sensitivity of 35 MHz/10 fold increase in creatinine concentration (during incubation) at the centre frequency of 6 GHz is gained by the immunosensor. The results are compared with a standard optical measurement technique and the dynamic range and sensitivity is of the order of the established optical indication technique. The C-band immunosensor chip comprising an area of 0.3 mm2 reduces the sensing area considerably, therefore, requiring a sample volume as low as 2 μl. The small analyte sample volume and label free approach also reduce the experimental costs in addition to the low fabrication costs offered by the batch fabrication technique of CMOS/BiCMOS process.
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    Multilevel HfO2-based RRAM devices for low-power neuromorphic networks
    (Melville, NY : AIP Publ., 2019) Milo, V.; Zambelli, C.; Olivo, P.
    Training and recognition with neural networks generally require high throughput, high energy efficiency, and scalable circuits to enable artificial intelligence tasks to be operated at the edge, i.e., in battery-powered portable devices and other limited-energy environments. In this scenario, scalable resistive memories have been proposed as artificial synapses thanks to their scalability, reconfigurability, and high-energy efficiency, and thanks to the ability to perform analog computation by physical laws in hardware. In this work, we study the material, device, and architecture aspects of resistive switching memory (RRAM) devices for implementing a 2-layer neural network for pattern recognition. First, various RRAM processes are screened in view of the device window, analog storage, and reliability. Then, synaptic weights are stored with 5-level precision in a 4 kbit array of RRAM devices to classify the Modified National Institute of Standards and Technology (MNIST) dataset. Finally, classification performance of a 2-layer neural network is tested before and after an annealing experiment by using experimental values of conductance stored into the array, and a simulation-based analysis of inference accuracy for arrays of increasing size is presented. Our work supports material-based development of RRAM synapses for novel neural networks with high accuracy and low-power consumption. © 2019 Author(s).
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    Charge pump design in 130 nm SiGe BiCMOS technology for low-noise fractional-N PLLs
    (München : European Geopyhsical Union, 2015) Kucharski, M.; Herzel, F.
    This paper presents a numerical comparison of charge pumps (CP) designed for a high linearity and a low noise to be used in a fractional-N phase-locked loop (PLL). We consider a PLL architecture, where two parallel CPs with DC offset are used. The CP for VCO fine tuning is biased at the output to keep the VCO gain constant. For this specific architecture, only one transistor per CP is relevant for phase detector linearity. This can be an nMOSFET, a pMOSFET or a SiGe HBT, depending on the design. The HBT-based CP shows the highest linearity, whereas all charge pumps show similar device noise. An internal supply regulator with low intrinsic device noise is included in the design optimization.
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    Self-calibrating highly sensitive dynamic capacitance sensor: Towards rapid sensing and counting of particles in laminar flow systems
    (Cambridge : Royal Society of Chemistry, 2015) Guha, S.; Schmalz, K.; Wenger, Ch.; Herzel, F.
    In this report we propose a sensor architecture and a corresponding read-out technique on silicon for the detection of dynamic capacitance change. This approach can be applied to rapid particle counting and single particle sensing in a fluidic system. The sensing principle is based on capacitance variation of an interdigitated electrode (IDE) structure embedded in an oscillator circuit. The capacitance scaling of the IDE results in frequency modulation of the oscillator. A demodulator architecture is employed to provide a read-out of the frequency modulation caused by the capacitance change. A self-calibrating technique is employed at the read-out amplifier stage. The capacitance variation of the IDE due to particle flow causing frequency modulation and the corresponding demodulator read-out has been analytically modelled. Experimental verification of the established model and the functionality of the sensor chip were shown using a modulating capacitor independent of fluidic integration. The initial results show that the sensor is capable of detecting frequency changes of the order of 100 parts per million (PPM), which translates to a shift of 1.43 MHz at 14.3 GHz operating frequency. It is also shown that a capacitance change every 3 μs can be accurately detected.
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    Atomically controlled CVD processing of group IV semiconductors for ultra-large-scale integrations
    (Bristol : IOP Publishing, 2012) Murota, Junichi; Sakuraba, Masao; Tillack, Bernd
    One of the main requirements for ultra-large-scale integrations (ULSIs) is atomic-order control of process technology. Our concept of atomically controlled processing is based on atomic-order surface reaction control by CVD. By ultraclean low-pressure CVD using SiH4 and GeH4 gases, high-quality low-temperature epitaxial growth of Si1−xGex (100) (x=0–1) with atomically flat surfaces and interfaces on Si(100) is achieved. Self-limiting formation of 1–3 atomic layers of group IV or related atoms in the thermal adsorption and reaction of hydride gases on Si1-xGex (100) are generalized based on the Langmuir-type model. By the Si epitaxial growth on top of the material already-formed on Si(100), N, B and C atoms are confined within about a 1 nm thick layer. In Si cap layer growth on the P atomic layer formed on Si1−xGex (100), segregation of P atoms is suppressed by using Si2H6 instead of SiH4 at a low temperature of 450 °C. Heavy C atomic-layer doping suppresses strain relaxation as well as intermixing between Si and Ge at the Si1−xGex/Si heterointerface. It is confirmed that higher carrier concentration and higher carrier mobility are achieved by atomic-layer doping. These results open the way to atomically controlled technology for ULSIs.
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    Interpolation algorithm for asynchronous ADC-data
    (Göttingen : Copernicus Publications, 2017) Bramburger, Stefan; Zinke, Benny; Killat, Dirk
    This paper presents a modified interpolation algorithm for signals with variable data rate from asynchronous ADCs. The Adaptive weights Conjugate gradient Toeplitz matrix (ACT) algorithm is extended to operate with a continuous data stream. An additional preprocessing of data with constant and linear sections and a weighted overlap of step-by-step into spectral domain transformed signals improve the reconstruction of the asycnhronous ADC signal. The interpolation method can be used if asynchronous ADC data is fed into synchronous digital signal processing.
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    Room temperature direct band gap emission from Ge p-i-n heterojunction photodiodes
    (London : Hindawi, 2012) Kasper, E.; Oehme, M.; Arguirov, T.; Werner, J.; Kittler, M.; Schulze, J.
    Room temperature direct band gap emission is observed for Si-substrate-based Ge p-i-n heterojunction photodiode structures operated under forward bias. Comparisons of electroluminescence with photoluminescence spectra allow separating emission from intrinsic Ge (0.8 eV) and highly doped Ge (0.73 eV). Electroluminescence stems fromcarrier injection into the intrinsic layer, whereas photoluminescence originates from the highly n-doped top layer because the exciting visible laser wavelength is strongly absorbed in Ge. High doping levels led to an apparent band gap narrowing from carrier-impurity interaction. The emission shifts to higher wavelengths with increasing current level which is explained by device heating. The heterostructure layer sequence and the light emitting device are similar to earlier presented photodetectors. This is an important aspect for monolithic integration of silicon microelectronics and silicon photonics.
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    Plasma enhanced complete oxidation of ultrathin epitaxial praseodymia films on Si(111)
    (Basel : MDPI, 2015) Kuschel, Olga; Dieck, Florian; Wilkens, Henrik; Gevers, Sebastian; Rodewald, Jari; Otte, Christian; Zoellner, Marvin Hartwig; Niu, Gang; Schroeder, Thomas; Wollschläger, Joachim
    Praseodymia films have been exposed to oxygen plasma at room temperature after deposition on Si(111) via molecular beam epitaxy. Different parameters as film thickness, exposure time and flux during plasma treatment have been varied to study their influence on the oxygen plasma oxidation process. The surface near regions have been investigated by means of X-ray photoelectron spectroscopy showing that the plasma treatment transforms the stoichiometry of the films from Pr2O3 to PrO2. Closer inspection of the bulk properties of the films by means of synchrotron radiation based X-ray reflectometry and diffraction confirms this transformation if the films are thicker than some critical thickness of 6 nm. The layer distance of these films is extremely small verifying the completeness of the plasma oxidation process. Thinner films, however, cannot be transformed completely. For all films, less oxidized very thin interlayers are detected by these experimental techniques.
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    Correction: Interface-engineered reliable HfO2-based RRAM for synaptic simulation (Journal of Materials Chemistry C (2019) DOI: 10.1039/c9tc04880d)
    (London [u.a.] : RSC, 2019) Wang, Qiang; Niu, Gang; Roy, Sourav; Wang, Yankun; Zhang, Yijun; Wu, Heping; Zhai, Shijie; Bai, Wei; Shi, Peng; Song, Sannian; Song, Zhitang; Xie, Ya-Hong; Ye, Zuo-Guang; Wenger, Christian; Meng, Xiangjian; Ren, Wei
    There was an error in the author list of this published article. The corresponding authors for this paper are Gang Niu (gangniu@xjtu.edu.cn) and Wei Ren (wren@mail.xjtu.edu.cn). The footnote indicating that Qiang Wang and Gang Niu contributed equally to the work was not intended. The corrected author list and notations are shown here. The Royal Society of Chemistry apologises for these errors and any consequent inconvenience to authors and readers. © The Royal Society of Chemistry 2019.
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    On the Impact of Strained PECVD Nitride Layers on Oxide Precipitate Nucleation in Silicon
    (Pennington, NJ : ECS, 2019) Kissinger, G.; Kot, D.; Costina, I.; Lisker, M.
    PECVD nitride layers with different layer stress ranging from about 315 MPa to −1735 MPa were deposited on silicon wafers with similar concentration of interstitial oxygen. After a thermal treatment consisting of nucleation at 650°C for 4 h or 8 h followed annealing 780°C 3 h + 1000°C 16 h in nitrogen, the profiles of the oxide precipitate density were investigated. The binding states of hydrogen in the layers was investigated by FTIR. There is a clear effect of the layer stress on oxide precipitate nucleation. The higher the compressive layer stress is the higher is a BMD peak below the front surface. If the nitride layer is removed after the nucleation anneal the BMD peak below the front surface becomes lower. It is possible to model the BMD peak below the surface by vacancy in-diffusion from the silicon/nitride interface. With increasing duration of the nucleation anneal the vacancy injection from the silicon/nitride interface decreases and with increasing compressive layer stress it increases. © The Author(s) 2019.